Lateral DMOS Research Articles

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80μm, the NBL PSOI LDMOS obtains a high BV of 1243V which is improved by around 105V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333K at a power (P) of 1mW/μm which is reduced by around 61K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.

Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage (BV). The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.

An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+is 1.3A and that with two floating P+is 2.7A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.

Advances in LDMOS Compact Modeling for IC Design: The SP-HV Model and Its Capabilities

Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are key interfaces between digital CMOS circuits and the real analog world; they are widely used in high-voltage and high-current applications, but they can be exceedingly difficult to model accurately. This article reviews recent advances in the compact modeling of LDMOS transistors, with an emphasis on the surface-potential-based high-voltage MOS (SP-HV) model and its capabilities. Detailed physical analysis of experimentally observed complexities in LDMOS behavior are reviewed and the relevance to IC design of the advanced modeling capabilities of SP-HV are detailed.

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Research and optimization of the ESD response characteristic in a ps-LDMOS transistor

The ESD response characteristic in a p-type symmetric lateral DMOS (ps-LDMOS) has been investigated. The experimental results show that the ps-LDMOS has weak ESD robustness due to an absence of the “snapback" characteristic. In addition, the location of the hot spot changes little for the special device. The method for reducing the lattice temperature of the hot spot can be used to enhance the ESD capacity of the ps-LDMOS, thereby, a novel and easily-achievable ps-LDMOS structure with a p-type lightly doped drain (p-LDD) has been proposed. The special region p-LDD lowers the electric field at the edge of the poly gate, making the whole distribution of the surface electric field more uniform. Therefore, the ESD robustness is improved two times and no obvious change of other electric parameters is introduced.

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.

Novel Bulk Silicon Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors Using Step Thickness Technology in Drift Region

In this paper, a novel bulk silicon lateral double-diffused metal–oxide–semiconductor field-effect transistors (LDMOS) using step thickness technology in drift region is proposed. The drift region is divided into several zones with different thicknesses increasing from source to drain. Owing to modulation effect of the step thickness drift region, new additional electric field peaks are introduced in the drift region, thus leading to the reduction of the surface electric fields and the increase of the breakdown voltage. The influences of device parameters on breakdown voltage and specific on-resistance are investigated using semiconductor device simulator, MEDICI. The simulation results indicate that an 18.4% increase in the breakdown voltage and a 42.5% increase in the figure of merit (FOM) are obtained in the novel device in comparison with the conventional LDMOS. Furthermore, single step can lead to approximately ideal FOM in comparison with the multiple steps, so that can obtain a suitable trade-off between fabrication costs and performance.

High-Voltage LDMOS Transistor With Split-Gate Structure for Improved Electrical Performance

An n-channel split-gate laterally double-diffused metal-oxide-semiconductor (LDMOS) device is presented. The proposed split-gate LDMOS has a primary gate (PG) and floating gate (FG). The FG is formed by spacer etching and placed along the perimeter of the PG. The potential of the FG is determined by the potential of the PG and the capacitive coupling ratio. Therefore, the FG has lower potential than that of the PG. This potential difference along the channel length direction accelerates channel carriers, which ultimately enhances device performances. From device measurements, the fabricated splitgate LDMOS devices showed improved electrical characteristics: lower drain-induced barrier lowering; higher transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ); lower drain conductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 1/ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rout</sub> ); lower ON-resistances R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ; and higher early voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EA</sub> = I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> .

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.

Design and Analysis of Power Low-Temperature Polysilicon Lateral Double-Diffusion Metal Oxide Semiconductor Field Effect Transistors with Shielding-Trench Structure

A new polycrystalline silicon (poly-Si) lateral double-diffusion metal oxide semiconductor field-effect transistor power device combining super-lateral-growth technology and shielding-trench oxide structures (STO-LDMOSFET) is introduced. The trench oxide offers a platform for amorphous silicon lateral growth through excimer laser annealing; this not only enables stable control of the crystallization of poly-Si but also promotes the blocking ability of devices. The breakdown voltages of the manufactured devices with and without trench oxide are 460 and 387 V, respectively, increasing by approximately 73 V. The characteristics of poly-Si treated with an excimer laser were obtained by low-temperature poly-Si LDMOSFET (LTPS-LDMOSFET) measurement and simulation. Then, STO-LDMOSFETs were studied by simulation. The results showed that the STO-LDMOSFET with a 150 cm2 V-1 s-1 mobility had a breakdown voltage and a specific on-resistance of approximately 450 V and 16 Ω cm2, respectively, at a 40 µm drift region length.

High-voltage super-junction lateral double-diffused metal—oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal—oxide semiconductor (SJ-LDMOS) with a partial lightly doped P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P− junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage (BV). In addition, due to the same conduction paths, the specific on-resistance (Ron,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal—oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced) surface field (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV) but also a significantly reduced Ron,sp. The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2. Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal—oxide semiconductor (LDMOS) with ultra-low specific on-resistance (Ron,sp) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce Ron,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, Ron,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

Model of hot‐carrier degradation for lateral IGBT device on SOI substrate

A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is presented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified.

On-Resistance Degradation Induced by Hot-Carrier Injection in SOI SJ-LDMOS

In this brief, anomalous hot-carrier degradation phenomenon in n-type superjunction lateral DMOS transistors on a SOI substrate is investigated. An unexpected on-resistance (Ron) decrease was observed at the beginning of stress, but Ron increases with the stress time. The reason was analyzed with the 3-D simulation of electrical field and impact ionization generation. The injection of hot holes into the field oxide near the drain region leads to the Ron decrease during the early stress period. With the increase of stress time, trapped hot holes accumulated in the field oxide and act as electron defects to trap electrons, altogether with hot electrons trapped in gate oxide above the accumulation region, contributing to Ron increase.