Lateral DMOS Research Articles

Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm

The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (Ron,sp) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and Ron,sp is less than the initial Ron,sp. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N+N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and Ron,sp. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

In this paper, a novel double-gate trench silicon-on-insulator lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (R on,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS, when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the R on,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/R on,sp) is increased by 397.2% from 3.6 MW cm−2 to 17.9 MW cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

In0.53Ga0.47As/In0.52Al0.48As Quantum Well Step Gate LDMOS to Improve the Device Performance

In this work, a new laterally double diffused metal oxide semiconductor (LDMOS) using In0.53Ga0.47As/In0.52Al0.48As Quantum well (QW) layer with a p-well step gate has been proposed. In the proposed device structure, the gate region splits into three steps in which the oxide thickness increases from the source to the drain end. As the gate insulator width varies from source to drain end, it results in better control of the gate over the channel and also a reduction in the gate-to-drain capacitance (CGD). These features offer higher transconductance with reduced switching delays, which makes the device appropriate for RF applications. Again, the concentration of current in the channel section is enhanced due to the presence of the Quantum well region and the InP spacer layer, which drastically reduces the On-resistance. But, the device achieves lesser gate-to-drain capacitance which results in decrease in the switching speed. On the other hand the proposed device offers less gate charge with the low value of CGD gives minimised switching loss. Based on 2D TCAD simulation, the proposed QW LDMOS exhibits 70% improvement in On-resistance, 45% in breakdown voltage, 84% improvement in peak transconductance, 26% improvement in switching delay, and 19% improvement in gate charge density as compared to conventional In0.53Ga0.47As devices.

4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

In this paper, we present a novel lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor for high-temperature and high breakdown voltage applications. The key idea in our study is replacing a 4H-SiC layer in a part of the buried oxide region (BOX) to reduce temperature effects. Moreover, the top of the 4H-SiC layer has multiple trenches to increase the breakdown voltage. These multiple trenches have been filled with an N-type silicon material. So, we call the proposed structures as multiple trenches 4H-SiC LDMOS (MTSiC-LDMOS). The proposed device is simulated by a two-dimensional ATLAS simulator, and we have shown that the maximum lattice temperature decreases and the breakdown voltage improves by optimization of multiple trenches in the 4H-SiC region. Also, the results show that the current flow and specific on-resistance have improved. Therefore, the MTSiC-LDMOS structure is more reliable than a conventional LDMOS (C-LDMOS) for high-temperature and high breakdown voltage applications.

Temperature Reliability Investigation for a 400 W Solid-State Power Amplifier under High and Cold Conditions

In order to study the temperature reliability of high-power amplifiers under high cand cold conditions, a 400 W solid-state power amplifier was taken as an example to explore the variation in its performance. The test results showed that its output power, gain, and power-added efficiency increased with the increase in temperature at a fixed frequency. Under a fixed input power, Pout and gain both showed different trends with the rising temperature. Within the frequency band of 2–10 MHz, the higher the temperature, the better the output power and gain. However, within the frequency range of 10–30 MHz, the higher the temperature, the worse the performance. Moreover, with the increasing temperature, its power-added efficiency, the second harmonic and the third harmonic also showed a decreasing trend. Detailed analysis showed that the degradation and inversion of performance parameters are closely related to the zero temperature coefficient and self-heating effect of the lateral double-diffused metal–oxide–semiconductor field-effect transistor. Meanwhile, it is also affected by the circuit structure and thermal design of the PA. In order to ensure stable performance in different environments, performance degradation can be improved by hardware compensation. Therefore, analyzing the working parameters at different temperatures for high-power PAs is the key to achieving temperature control and ensuring their long-term stability and reliability. This can provide relatively accurate reference data for subsequent heat dissipation optimization, greatly improve design efficiency, and even shorten the development cycle and reduce costs.

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (R on,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases R on,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the R on,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 /R on.sp) increases remarkably from 2.15 MW·cm−2 to 18.13 MW·cm−2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

A novel substrate Voltage-assisted RESURF technique in SOI LDMOS with a heavily doped drift region

A novel substrate voltage-assisted (SVA) reduced surface field (RESURF) technique in SOI lateral double-diffused Metal-Oxide-Semiconductor (LDMOS) with a heavily doped drift region is proposed. Without any additional masks and processes, an external control circuit is designed to adaptively control the substrate voltage in the technique. The co-simulation based on TCAD and the circuit is implemented to explore the mechanism of the SVA RESURF technique. In the off-state, a negative bias is applied to the substrate, which induces positive charges to compensate for the heavily doped ionizing acceptors in the drift region. The breakdown voltage is improved and remains at the same level as the conventional RESURF device. In the on-state, a zero bias is applied to the substrate, and heavy doping in the drift region can achieve low specific on-resistance compared to the RESURF device with a lightly doped drift region. As a result, the proposed technique reconstructs the charge balance and the conventional RESURF condition. The simulation results show reduced specific on-resistance, low drain leakage current, large saturation current, high transconductance and cut-off frequency, decreased turn-on/off characteristics and improved FOM and BFOM compared with the conventional RESURF technique. Furthermore, an analytical model is developed to optimize the substrate voltage for the maximum breakdown voltage in the external control circuit design of the proposed technique.

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

The silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) with high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{k}$</tex-math> </inline-formula> multi-fingers (HKMFs) is proposed and investigated. The fingertips are distributed at specific locations to modulate the electric field distributions and improve the device performances. First, the electric field peaks formed at the fingertips could optimize the electric field distributions, which improves the breakdown voltage (BV) of the LDMOS effectively. Meanwhile, the multi-fingers are embedded into the drift region to increase the optimal drift doping concentration, which facilitates the positive conduction of the device and reduces the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on,\text{sp}}}\text{)}$</tex-math> </inline-formula> . The simulation results show that the proposed HKMF-LDMOS with five multi-fingers increases the BV by 59.2%, reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on,\text{sp}}}$</tex-math> </inline-formula> by 37.8%, and improves the figure of merit (FOM) by 4.07 times when compared to the conventional LDMOS.

A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77–300 K temperature range and demonstrates excellent scalability.

Study of TID radiation effects on the breakdown voltage of buried P-pillar SOI LDMOSFETs with P-top region

This article presents the numerical investigation on the total ionizing dose (TID) radiation induced breakdown voltage shifting behavior of the silicon-on-insulator (SOI) buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) with a P-top region (TP). We validate the employed simulation models and structure parameters by the experiments of the 200 V rated SOI BP-LDMOS devices. We also discuss the breakdown voltage (BV) analysis of the SOI BPTP-LDMOS under different doping concentrations in the drift region. Because the lateral breakdown voltage can be effectively enhanced by the P-top region under STI layer, the SOI BPTP-LDMOS behaves a wider Nd window for rated 200 V compared with the SOI BP-LDMOS. Finally, we perform the numerical investigation of the TID radiation effect on the BV shift. Using the TID hardening design with the electric field modulation method, the hardened BPTP-LDMOS can achieve a significant improvement in the TID tolerance compared with the hardened SOI BP-LDMOS, from 575 to 775 krad(Si).

Test Structure Design for Defect Detection during Active Thermal Cycling.

Integrated power ICs acting as smart power switches for automotive or industrial applications are often subjected to active thermal cycling. Consequently, they undergo significant self-heating and are prone to various failure mechanisms related to the electro-thermo-mechanical phenomena that take place in the device metallization. In this article a test structure consisting of a lateral DMOS transistor equipped with several integrated sensors is proposed for metallization fatigue assessment. The design of the test structure is presented in detail, alongside with design considerations drawn from the literature and from simulation results. The testing procedure is then described, and experimental results are discussed. The experimental data provided by the integrated sensors correlated with the electro-thermal simulation results indicate the emergence of a failure mechanism and this is later confirmed by failure analysis. Conclusions are further drawn regarding the feasibility of using the proposed integrated sensors for monitoring defects in power ICs.

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

In thsi paper a novel optimum variation lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and numerically simulated. For the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region; thus the doping concentration of the n-drift region can be significantly increased, resulting an ultra-low specific resistance (R on,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. The current saturation characteristic, gate–drain capacitance (C GD) and gate-to-drain charge (Q gd) of the proposed device are all improved, thanks to the effect of the source-connected p-top region. Compared with a conventional LDMOS, the numerical simulation results show that the BV, R on,sp and Q gd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. The three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be produced by one-time fabrication process, which brings great convenience to future production.

A Steady-State LDMOST Model Based on Semi-Numerical Regional Approach

This paper presents a high-voltage lateral DMOS transistor (LDMOST) model for steady-state condition.The device modelling method is basically based on a semi-numerical regional approach.The complete model is physical, so that it accounts for unique LDMOST features such as non-uniform channel doping, non-planar drift region and space-charge-limited current flowing.Themodelcalculationsshow good overall agreement withthe measured results.This DMOS transistor model, whichcan beapplicable to a SPICE-like circuit simulator, might be useful in technology CAD of high-voltage power ICs.

Novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with low specific on-resistance by super junction layer

A novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor (LDMOS) field effect transistor with the low specific on-resistance (Ron,sp) by super-junction (SJ) layer (Si/SiC SJ-LDMOS) is proposed in this paper. On the basis of using N-Buffer layer to solve substrate assisted depletion effect (SAD), breakdown point transfer terminal technology (BPT) is realized by the deep drain structure of Si/SiC heterojunction and electric field modulation is carried out, which further improves the breakdown voltage (BV) of Si/SiC SJ-LDMOS, alleviates the contradictory relationship between the BV and the Ron,sp. Through ISE TCAD simulation, the result shows that with the same drift region length of 20 μm, the BV is increased from 114 V of conventional SJ-LDMOS (Cov. SJ-LDMOS) and 270 V of SJ-LDMOS with N-Buffer layer (Buffer SJ-LDMOS) to 374 V of Si/SiC SJ-LDMOS, increased by 228% and 38%, respectively. In addition, the Ron,sp of Cov. SJ-LDMOS, Buffer SJ-LDMOS and Si/SiC SJ-LDMOS are 46.26 mΩ cm2, 26.96 mΩ cm2 and 25.85 mΩ cm2, respectively. Moreover, the figure-of-merit (FOM) of proposed Si/SiC SJ-LDMOS device is 5.411 MW/cm2, which means the Si/SiC SJ-LDMOS has a better performance to break the silicon limit. The influence of design parameters on device performance is also discussed.

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

Study of TID Radiation Effects on the Breakdown Voltage of Buried P-Pillar SOI LDMOSFETs

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on,sp</sub> ) of the SOI BP-LDMOS is 9.5 mΩ· cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si).

Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region

Abstract Heterojunction terminal technology, especially Si/SiC heterojunction, has been widely used in the power semiconductor device. Si/SiC heterojunction LDMOS combines the advantages of Si and SiC while the breakdown point is transferred due to employing the deep drain region structure to improve the BV of the device. Based on the existing research, a new theory about breakdown point transfer terminal technology is proposed for silicon on silicon carbide lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region based on the electric field modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the breakdown voltage and electric field (E-field) distributions of Si/SiC LDMOS. The mechanism of surface electric field modulated and optimized by breakdown point transfer terminal technology is explained. Introducing the drain region impact factor into the analytical model to decouple the lateral and vertical depletion below the drift region. The analytical model proves that the deep drain region structure can modulate both the lateral and vertical electric field. Meanwhile, the location of the breakdown point can be determined by the E-field distribution at y = TDr and the E-field distribution at y = TSi, which is demonstrated by both theoretical interpreting and simulation. The derivations were verified using the ISE TCAD with a good agreement in the analytical model by changing the key structural parameters of the device. This analytical theory can be applied to other heterojunction power devices.

A Novel Deep Gate LDMOS Structure Using Double P-Trench to Improve the Breakdown Voltage and the On-State Resistance

To increase the breakdown voltage and reduce the on-state resistance, a novel Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) field-effect transistor is proposed in this paper. In the proposed structure, double P-trenches are inserted in the buried oxide under the source and drain regions. The proposed device is called as the double p-trench deep gate LDMOS (DPTDG-LDMOS). By optimizing the P-trenches, the electric field will be more uniform, and so the maximum breakdown voltage obtains. Our simulation results show that the breakdown voltage, on-state resistance, maximum temperature (TMAX), and figure of merit (FOM) for the DPTDG-LDMOS are improved in comparison with a conventional LDMOS.

Analysis of novel silicon based lateral power devices with floating substrate on insulator

With the rapid development of the traditional inorganic semiconductor industry, the improvement of its electrical performance is gradually approaching to the limit. It is difficult to continue to improve the performance, lessen the size, and reduce the cost. Therefore, organic semiconductor materials and devices with simple process and low cost have been found and gradually become a new research hotspot. Although organic semiconductor materials and devices are developing rapidly, their electrical properties, such as carrier mobility, are considerably inferior to those of inorganic semiconductors, and their research direction and application prospect are relatively fixed and single. They are developed only in display, sensing, photoelectric conversion and other fields, but the researches on switching power devices, integrated circuits and other fields are still relatively blank. At the same time, power devices are used only in the field of inorganic semiconductors. Therefore, in order to expand the research direction of organic semiconductors and power devices at the same time, a novelsilicon on insulator lateral double-diffused metal oxide semiconductor (SOI LDMOS)power device is reported in this paper. Unlike the SOI LDMOS power devices in traditional inorganic semiconductors, this novel device can be used in the field of organic semiconductors by combining with insulated flexible substrates, which provides a new possibility for the research direction of organic semiconductors. In this paper, both simulation and experiment verify that specific on-resistance (&lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt;) and threshold voltage (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;) do not change significantly when the conventional SOI LDMOS lacks the substrate electrode, but the breakdown voltage decreases by about 15% due to the absence of the substrate electrode or the longitudinal electric field. In response to this phenomenon, in this paper proposed is a novel SOI LDMOS power device that possesses surface substrate electrodes and drift zone oxide trenches. This novel device can provide electrodes for the substrate again, optimize the horizontal and vertical electric field, and significantly change neither of the &lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt; and the &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;. At the same time, the breakdown voltage (BV) of conventional SOI LDMOS is increased by 57.54%, which alleviates the adverse effects caused by the application in the field of organic semiconductors. This novel SOI LDMOS power device provides the possibility of applying traditional power semiconductors to the research of organic semiconductors, and has innovative significance for expanding the organic semiconductor research.