Lateral Charge Migration Research Articles

Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash

With the rising security concern on modern storage systems, the concept of data sanitization has been widely investigated recently. Among the existing works targeting data sanitization, an overwriting-based approach, namely one-shot sanitization, is one of the most efficient sanitization approaches. Nonetheless, we find that the one-shot sanitization approach would fail to achieve precise data sanitization for 3D TLC NAND flash, because of incurring undesired data errors. That is, how to simultaneously realize precise sanitization and high security with decent latency and reliability on emerging storage devices remains unsolved. This work proposes an elaborate sanitization design that skillfully manipulates the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> ) distribution of sanitized pages. Not only does the proposed design achieve precise sanitization and high security, but it also enhances read performance and data reliability. Specifically, this work elaborately sanitizes data by merging specific <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> distributions of the target physical page on 3D TLC NAND flash. Besides, the proposed approach further takes lateral charge migration into consideration to improve data reliability. We conduct a series of experiments to evaluate our proposed approach on real 3D TLC NAND flash. The experiment results demonstrate the proposed approach can achieve elaborate data sanitization under various scenarios and improve read performance by 29%.

Lateral charge migration in 1D semiconductor-metal hybrid photocatalytic systems.

Colloidal nanorods based on CdS or CdSe, functionalized with metal particles, have proven to be efficient catalysts for light-driven hydrogen evolution. Seeded CdSe@CdS nanorods have shown increasing performance with increasing rod length. This observation was rationalized by the increasing lifetime of the separated charges, as a large distance between holes localized in the CdSe seed and electrons localized at the metal tip decreases their recombination rate. However, the impact of nanorod length on the electron-to-tip localization efficiency or pathway remained an open question. Therefore, we investigated the photo-induced electron transfer to the metal in a series of Ni-tipped CdSe@CdS nanorods with varying length. We find that the transfer processes occurring from the region close to the semiconductor-metal interface, the rod region, and the CdSe seed region depend in different ways on the rods' length. The rate of the fastest process from excitonic states generated directly at the interface is independent of the rod length, but the relative amplitude decreases with increasing rod length, as the weight of the interface region is decreasing. The transfer of electrons to the metal tip from excitons generated in the CdS rod region depends strongly on the length of the nanorods, which indicates an electron transport-limited process, i.e., electron diffusion toward the interface region, followed by fast interface crossing. The transfer originating from the CdSe excitonic states again shows no significant length dependence in its time constant, as it is probably limited by the rate of overcoming the shallow confinement in the CdSe seed.

Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory

3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively.

Stability of Charge Distributions in Electret Films on the nm-Scale.

Electret materials find use in various applications, such as microphones or filter media. In recent years, electrets have been used also increasingly on the micrometer scale, for example, in MEMS or for nano-xerography. However, for these applications, it becomes more important to prepare defined charge structures with sub-micrometer features. On the macroscopic level, the technique of isothermal potential decay at elevated temperatures has been developed to study aging effects and charge retention capabilities in electret materials. Here, we extend this technique to the nm-level by means of AFM-based methods, such as contact charging by AFM and the Kelvin probe force microscopy. Defined charge distributions in polyetherimide (PEI) ULTEM 1000 thin-film electrets have been studied for the first time with a high lateral resolution on the nanometer scale. We found a linear correlation between externally applied contact charging potential on the AFM-tip and the resulting relative surface potential on the PEI film. Charge decay at elevated temperatures is independent from the length scale. The same time dependence as for macroscopic, homogenously charged films could be established. We observe a potential decay only at an elevated temperature of 120 °C and no significant lateral charge transport. Thus, we propose a thermally enhanced charge carrier release from surface traps and a subsequent charge migration to the back electrode as the dominant mechanism. This finding is in-line with the observation that potential decay can be reduced also on the nm-level by pre-annealing the film slightly below the glass transition temperature. In contrast to many polymeric or inorganic electrets, no lateral charge migration is observed. Therefore, the charge patterns are preserved for PEI ULTEM 1000 thin-film electrets, which makes it a good candidate as electret for applications in MEMS or similar applications.

Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing

This article proposes a privacy-aware data-lifetime control NAND flash system (PDLCS) that changes the data-lifetime flexibly for privacy protection. The proposed PDLCS consists of four proposed techniques: 1) inverse Huffman-coding ${V}_{{\text {TH}}}$ modulation (IHVM); 2) immediate delete command (IDC); 3) adaptive lifetime extension (ALE); and 4) adaptive lifetime reduction (ALR), with In-3-D vertical cell processing of 3-D NAND flash memories. This system realizes both short- and long-term data lifetimes. Furthermore, data lifetime can be extended or shortened at any time. This cannot be realized by conventional 2-D NAND flash memories because data lifetime is controlled by the lateral charge migration in 3-D NAND flash memories. The proposed PDLCS secures privacy data and, thus, is a universal solution for future secure storage, which is not resolved by software techniques.

Lateral charge migration induced abnormal read disturb in 3D charge-trapping NAND flash memory

Abnormal read disturb (RD) has been investigated in three-dimensional (3D) charge-trapping NAND flash memory. Similar to traditional 2D NAND, RD will cause more error bits right after programming. However, after short-time retention, it has weak effects on error bits; more importantly, after long-time retention, a part of error bits can be recovered. With special coding designs in chip characterizations and TCAD simulations, it is concluded that lateral charge migration could be dominant mechanism for abnormal RD, which can be utilized to prolong lifetime of 3D NAND-based memory system for cold storage applications.

Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory

As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this work. According to experimental analysis and TCAD simulation, it is found that, in vertically scaled 3D NAND, the vertical charge loss is deteriorated not only by the cycling induced tunnel oxide degradation (introducing interface/oxide traps), but also by the cycling induced intercell trapped charge (enhancing word-lines edge electric field), on account of the enhanced Poole-Frenkel effect and tunneling effect. On the other hand, the cycling induced intercell trapped charge can also suppress lateral charge migration. Therefore, the vertical charge loss, rather than the lateral charge migration, still can be the dominant factor for post-cycling retention characteristics in scaling Lg/Ls 3D NAND flash memory.

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Adaptive artificial neural network (ANN)coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D and 2-D, charge-trap and floating-gate NAND flash memories. In 3-D NAND flash, lateral charge migration, vertical charge de-trap, inter floating-gate capacitive coupling noise, and inter word-line variations cause errors. On the other hand, in 2-D NAND flash, the charge de-trap and the harsh inter floating-gate capacitive coupling of adjacent word-lines and bit-lines cause errors. To solve these reliability problems, the proposed ANN automatically and adaptively compensates for complex memory cell errors. Moreover, the proposed ANNLDPC can reproduce the dynamic endurance and data-retention time dependence of errors. In addition, this paper evaluates the impacts of the chip-to-chip variations on the proposed ANN-LDPC. The proposed ANN-LDPC is implemented in the storage controller and can precisely and adaptively estimate bit-error rate (BER) and log-likelihood ratio (LLR). By using the precise LLR, LDPC decoder effectively corrects errors. As a result, ANN-LDPC extends the acceptable data-retention time by over 76× and 45× compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) ECC in 3-D and 2-D triple-level cell (TLC) NAND flash memories, respectively.

Analysis of the Retention Characteristic in Three dimensional Junction-less Charge Trapping Memory

This work studied the retention characteristic of three dimensional cylindrical junction-less charge trapping memory. Both trapped charge and electron concentration distributions along the channel direction are observed by using sentaurus 3D device simulator. Lateral charge migration is significant after programming with 10 years retention. For vertical direction, charge loss toward block layer is more serious than tunnel layer. Nearly no trapped hole loss even after erasing 10 years.

Analysis of the Retention Characteristic in Three dimensional Junction-less Charge Trapping Memory

To meet the storage requirement of big data, charge trap concept-based three dimensional charge trapping memory (3D-CTM) becomes the main trend of flash technology development. With the multi-layer gate stacking, the equivalent technology node can be scaled down to 10nm without the serious reliability problems from cell-to-cell coupling and SILC-inducing charge loss in conventional flash memory. Specially, the cylindrical junction-less structures such as BICS and TCAT have attracted extensive attention from academia and industry due to their merits of relatively simple procedure and full compatibility with the CMOS process. Moreover, the vertical channel and the ring shape gate stack of memory cell make the 3D memory show superior program/erase performance comparing with the conventional planar flash. However, the shape of charge trap layer is also an important factor affecting the device reliability. The uneven electrical field distribution in tunnel and block layer and the non-separated charge trapping layer of the cylindrical junction-less geometry bring some problems about charge lose in program or erase state. The retention is a critical issue for high density and reliability of 3D integration. In this work, the retention characteristic of 3D cylindrical junction-less charge trapping memory has been investigated. The trapped charge and electron concentration distribution after programming/erasing 10 years have been simulated by sentaurus 3D device simulator. The lateral and vertical charge migrations also have been discussed during the charge losing process. Furthermore, the dominant loss path at the vertical direction has been considered. Figure 1(a) shows schematic birds-eye view of typical 3D-CTM array structure. In order to study the retention properties of 3D vertical memory cell, a string with one cell and two select transistors is used in simulation, as shown in Figure 1(b). Sentaurus 3D device simulator was used for the simulation. The barrier tunneling model contains Fowler–Nordheim tunneling and direct tunneling components, which depends on the energy barrier and band bending calculated self-consistently. From the simulate result of trapped charge at the initial programmed state (initial state) and 10 years after programming state under 85°C condition (10 years state), it can be found that the lateral charge migration happened at 10 years state with respect to the initial state. And the lateral extention distance will be longer if the vertical charge loss is unconsidered. Also,the simulate result shows there is a competition between vertical and lateral charge loss and the vertical charge loss weaken the lateral charge migration during the retention time. Then, the dominant loss path at the vertical direction has been studied. We find that charge loss toward block layer is more serious than tunnel layer. The retention at erase state is also be investigated.Comparing with electron loss, the trapped hole nearly doesn’t loss even after 10 years. This simulation result coincides with the experiment data from Toshiba and Samsung. It’s can be attributed to the larger effective mass and deeper trap energy level of the hole, making it harder to occur tunneling and migration. In this article, retention of 3D cylindrical junction-less CTM has been studied. For the programmed device, lateral charge migration is obvious after 10 years. Vertical charge loss also occurs and lose more seriously toward block layer than tunnel layer. For the erased device, there is nearly no trapped hole loss even after 10 years. This work was supported by the National Natural Science Foundation of China (Grant No. 61474137, No. 61306107, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404). Figure 1

Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory**Project supported by the National Natural Science Foundation of China (Nos. 61474137, 61176073, 61306107).

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

Assessment methodology of the lateral migration component in data retention of 3D SONOS memories

A new procedure to assess the impact of lateral charge migration from the overall retention transient is developed. This experimental procedure is designed to be applied on any 3D NAND string, and does not require devices specifically designed; this allows to assess the impact of lateral migration in realistic conditions. The experimental procedure relies on comparing retention loss of a standard sample with a “control sample” not suffering from lateral migration, thanks to a pre-conditioning operation. The pre-conditioning procedure to obtain the control samples is discussed in detail and demonstrated through measurements and simulations.

Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices

This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices reveal an important contribution of lateral charge migration at 150°C and are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. This new model was used to simulate 3D vertical SONOS devices, where multiple cells are stacked in a cylindrical structure and process constrains the adoption of a self-aligned charge storage layer. A string of three cells and two select transistors has been simulated, evaluating, for different channel length and temperatures, the impact on string operations of the charge migrating in the nitride located between different gates.

Novel two-bit HfO/sub 2/ nanocrystal nonvolatile flash memory

This paper presents a novel nonvolatile poly-Si-oxide-nitride-oxide-silicon-type Flash memory that was fabricated using hafnium oxide (HfO/sub 2/) nanocrystals as the trapping storage layer. The formation of HfO/sub 2/ nanocrystals was confirmed using a number of physical analytical techniques, including energy-dispersive spectroscopy and X-ray photoelectron spectroscopy. These newly developed HfO/sub 2/ nanocrystal memory cells exhibit very little lateral or vertical stored charge migration after 10k program/erase (P/E) cycles. According to the temperature-activated Arrhenius model, we estimate that the activation energy lies within the range 2.1-3.3 eV. These HfO/sub 2/ nanocrystal memories exhibit excellent data retention, endurance, and good reliability, even for the cells subjected to 10 k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile Flash memory applications.

Transient absorption measurements of acceptor–sensitizer–donor triad molecules in solutions and Langmuir–Blodgett films

Transient absorption measurements of an acceptor–sensitizer–donor (A–S–D) triad molecule (ASD) that contained viologen, pyrene, and ferrocene as the A, S, and D moieties, respectively, were made in benzonitrile and aqueous micellar solutions, and in a Langmuir–Blodgett (LB) monolayer assembly. Intramolecular electron transfer reactions were initiated by photo-excitation of the S moiety, which gave rise to the long-lived final charge-separated A −–S–D + state. The rate of the backward electron transfer from A − to D + was determined from the absorption decay of the viologen cation radical monitored at 600–700 nm. The estimated lifetime of the final charge-separated state was ca. 60 ns, based on measurements of the solutions. Extremely slow decay (much longer than 600 μs) of the transient absorption of the viologen cation radical was observed for a mixed ASD LB film with 22-tricosenoic acid (TA). This slow decay observed on a LB film at higher ASD concentrations may be explained by lateral charge migration between adjacent molecules in the monolayer plane.

Computer model of the trapping media in micro FLASH® memory cells

A computer model for the dielectric trapping layer in the microFLASH memory transistor is developed. Due to local trapping of injected charges in corresponding devices the problem of lateral charge migration in the plane parallel to the transistor channel becomes of principal importance. Molecular Dynamics method was used to design a cluster of atoms with dielectric properties and to perform computer simulation of the redistribution of the injected charges in the program/erase processes. The charge distributions obtained on the basis of proposed model are strongly influenced by Coulomb repulsion between the trapped charge carriers. This effect leads to non-Gaussian discrete space distribution of trapped charges and significantly influences the endurance of the memory device. We demonstrate that large densities of traps and injected carriers are strongly correlated, limiting the amount of charge that can be accumulated in the programming process. The model allows select optimum parameters of the trapping layer to ensure high retention properties of the memory cells.