Latency Overhead Research Articles

A user application-based access point selection algorithm for dense WLANs.

The current commercial access point (AP) selection schemes are mostly based on received signal strength, but perform poorly in many situations. To address this problem, a number of alternative schemes collect and analyze the actual load of every candidate AP. However, these schemes may incur significant latency and signaling overhead in dense wireless local area networks (WLANs). To mitigate such overhead, we propose a user application-based AP selection scheme that considers historical information about AP performance. Without inducing any signaling activity, our scheme monitors the amount of network traffic used by applications and estimates the achievable throughput of APs. Our scheme employs the characteristics of application traffic with the intent of accurately predicting AP performance. Using a measurement study in dense WLAN environments, we show that our scheme achieves higher throughput and lower association latency than those of existing schemes in places highly accessible to the user.

AccConF: An Access Control Framework for Leveraging In-Network Cached Data in the ICN-Enabled Wireless Edge

The fast-growing Internet traffic is increasingly becoming content-based and driven by mobile users, with users more interested in data rather than its source. This has precipitated the need for an information-centric Internet architecture. Research in information-centric networks (ICNs) have resulted in novel architectures, e.g., CCN/NDN, DONA, and PSIRP/PURSUIT; all agree on named data based addressing and pervasive caching as integral design components. With network-wide content caching, enforcement of content access control policies become non-trivial. Each caching node in the network needs to enforce access control policies with the help of the content provider. This becomes inefficient and prone to unbounded latencies especially during provider outages. In this paper, we propose an efficient access control framework for ICN, which allows legitimate users to access and use the cached content directly, and does not require verification/authentication by an online provider authentication server or the content serving router. This framework would help reduce the impact of system down-time from server outages and reduce delivery latency by leveraging caching while guaranteeing access only to legitimate users. Experimental/simulation results demonstrate the suitability of this scheme for all users, but particularly for mobile users, especially in terms of the security and latency overheads.

FCR: Fast and Consistent Controller-Replication in Software Defined Networking

We consider the problem of coordination among replicated SDN controllers, where the challenge is to ensure a consistent view of the network while reacting to network events in a prompt manner. Existing solutions are either consensus-based, which achieve consistency at the expense of high latency; or eventual-consistency-based, which have low latency at the expense of severe limitations on the types of applications and policies implementable by the controller. We propose the Fast and Consistent Controller-Replication (FCR) scheme. FCR is based on a deterministic agreement mechanism that performs agreement on the input of controllers, instead of agreement on the output as done in consensus mechanisms. We formally prove that FCR provides the same guarantees in terms of implementable applications and network policies, as any deterministic single-image controller. Through simulation and implementation, we show that these guarantees can be implemented with little latency overhead, compared to eventual-consistency approaches, and can be achieved significantly faster than consensus-based approaches.

Optimized 3D Deployment of UAV-Mounted Cloudlets to Support Latency-Sensitive Services in IoT Networks

The paradigm of Internet of Things (IoT) is transforming physical environments into smart and interactive platforms to offer a wide range of innovative services supported by the evolution towards 5G networks. A major class of emerging services relies on highly intensive computations to make real-time decisions with ultra-low latency. Edge computing has been established as an effective approach to reduce the latency overhead of cloud computing and effectively augment the computational capabilities of IoT devices. In this work, we leverage the mobility and agility of Unmanned Aerial Vehicles (UAVs) as mobile edge servers or cloudlets to offer computation offloading opportunities to IoT devices. In particular, we consider the joint problem of optimizing the number and positions of deployed UAV cloudlets in 3D space and task offloading decisions with cooperation among UAVs, in order to provision IoT services with strict latency requirements. We formulate the problem as a mixed integer program, and propose an efficient meta-heuristic solution based on the ions motion optimization algorithm. The performance of the meta-heuristic solution is evaluated and compared to the optimal solution as a function of various system parameters and for different application use cases. It is shown to achieve near-optimal performance with low complexity and, thus, can efficiently scale up to large IoT network scenarios.

WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing Applications

Using a hybrid main memory in embedded systems to process image processing applications has become an irresistible trend. However, the performance deficiencies (less write endurance and relative longer write latency) in phase change memory (PCM) have become the bottleneck for performance improvement in the whole system. To further improve the performance in the hybrid memory system, data migration schemes have been put forward to migrate the sequential data between DRAM and PCM. Nevertheless, the existing schemes are always universal type page migration schemes, which cannot be aware of the write hot pages in image processing applications accurately. In addition, a large number of unnecessary page migrations occurring has the potential to increase the latency overhead of page management and destroy the locality of the applications leading to performance degradation. In this paper, focusing on the image processing applications, we present a better estimator in predicting the future memory writes: inter-reference distance with history writes frequency. Based on this observation, we present a novel page migration scheme for hybrid DRAM and PCM memory architecture called write frequency with inter-reference distance (WIRD). The scheme monitors access patterns, migrates pages between DRAM and PCM relying on the memory controller. The experimental results show that our scheme minimizes the unnecessary page migrations which make most of the write hot pages absorbed by DRAM efficiently. Meanwhile, the high-efficiency character of WIRD has decreased the write to read switching ratio in the system which makes the PCM effective page write access time reduced to a large extent.

Safe and efficient power management of hard real-time networks-on-chip

The power overhead of Networks-on-Chip (NoCs) becomes tremendous in high density Multiprocessor Systems-on-Chip (MPSoCs). Especially in hard real-time and safety-critical systems, power management mechanisms must be developed and efficiently adhered to real-time requirements. However, state-of-the-art solution typically induces a high timing overhead, thus challenging safety, or has limited power saving capabilities. Additionally, current power-gating mechanisms do not provide an upper bound of the latency overhead, and thus no timing guarantees. We propose a safe and enhanced approach for power-gating that allows a global and dynamic power management under timing guarantees, i.e., all deadlines of critical tasks are met. It introduces a control-layer to save power on the NoC data layer using multiple Power-Aware Traffic-Monitor (PATM) units, which apply knowledge of the global state of the system to efficiently save power on NoC routers even at high NoCs utilizations. To safely apply the PATMs in hard real-time systems while meeting the deadlines, we provide a formal worst-case timing analysis to derive PATMs upper bound latency overhead. Experimental results show that our approach efficiently reduces static power consumption, and provides scalability inducing very small area overhead.

Low-Power Scalable 3-D Face Frontalization Processor for CNN-Based Face Recognition in Mobile Devices

A low-power scalable 3-D face frontalization processor is proposed for accurate face recognition in mobile devices. In spite of recent improvement in face recognition accuracy mainly from convolutional neural networks (CNNs), their performance is limited to face images with frontal view. For face recognition with human-level accuracy in real-life environment, in which most of the face images are captured from arbitrary angles, 3-D face frontalization is essential as a preprocessing stage for CNN-based face recognition algorithms. The proposed face frontalization processor shows scalability in two aspects: image resolution and accuracy. For low-power consumption and scalability, the processor proposes three features: 1) scalable processing element (PE) architecture with workload adaptation; 2) accuracy scalable regression weight quantization to reduce the external memory access (EMA) down to 81.3%; and 3) pipelined memory-level zero-skipping to further reduce the EMA by 98.4% without any latency overhead. From the proposed EMA reduction features, the EMA is reduced by 99.7% with little accuracy degradation in face frontalization results. The proposed face frontalization processor is implemented in 65-nm CMOS process, and it shows 4.73 frames/s) throughput. Moreover, power consumption of the implemented face frontalization processor is 0.53 mW, which is suitable for applications on mobile devices.

Performance Characterization of NVMe-over-Fabrics Storage Disaggregation

Storage disaggregation separates compute and storage to different nodes to allow for independent resource scaling and, thus, better hardware resource utilization. While disaggregation of hard-drives storage is a common practice, NVMe-SSD (i.e., PCIe-based SSD) disaggregation is considered more challenging. This is because SSDs are significantly faster than hard drives, so the latency overheads (due to both network and CPU processing) as well as the extra compute cycles needed for the offloading stack become much more pronounced. In this work, we characterize the overheads of NVMe-SSD disaggregation. We show that NVMe-over-Fabrics (NVMe-oF)—a recently released remote storage protocol specification—reduces the overheads of remote access to a bare minimum, thus greatly increasing the cost-efficiency of Flash disaggregation. Specifically, while recent work showed that SSD storage disaggregation via iSCSI degrades application-level throughput by 20%, we report on negligible performance degradation with NVMe-oF—both when using stress-tests as well as with a more-realistic KV-store workload.

Analog to Sequence Converter-Based PAM-4 Receiver With Built-In Error Correction

This paper describes an energy-efficient pulse-amplitude modulation (PAM)-4 digital receiver based on sequence detection. The proposed scheme exploits the pre-cursor ISI in the channel to reconstruct a time series of a 5-bit sequence including future MSB. The future MSB information is used to detect and correct error in the current symbol detection with minimal power and latency overhead. This concept is demonstrated with prototype implemented in a 28-nm fully-depleted silicon-on-insulator CMOS using 18-data comparators. Consuming only 82 mW at 28 Gb/s, the receiver can compensate up to 27-dB channel loss with bit error rate (BER) lower than 10−8. With error correction, the receiver can achieve BER lower than 10−10.

Mapping of lattice surgery-based quantum circuits on surface code architectures

Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to ∼86%) and latency overhead (up to ∼79%).

Lifetime-aware scheduling in high level synthesis

Among various reliability challenges, accelerated aging is of particular importance. The flexibility of high-level synthesis (HLS) can be employed at an affordable cost to increase the reliability, and in particular lifetime, of the systems. In this paper, we extract the aging characteristics of the functional units (FUs), then, a scheduling method based on integer linear programming (ILP) is proposed to increase the lifetime, using the aging characteristics of the FUs. The proposed method extends the lifetime beyond the minimum expected value, with the minimum latency overhead, by applying the operation chaining and multicycling techniques in an aging-aware approach. The constraint matrix of the proposed ILP formulation is totally unimodular. This technique is suitable for both data-flow intensive and control-flow intensive designs and is applicable for large circuits. Experimental results show that the proposed approach increases the lifetime by 2.33×, and increases the latency by an average of 19.8%.

Optimizing nonzero-based sparse matrix partitioning models via reducing latency

For the parallelization of sparse matrix–vector multiplication (SpMV) on distributed memory systems, nonzero-based fine-grain and medium-grain partitioning models attain the lowest communication volume and computational imbalance among all partitioning models. This usually comes, however, at the expense of high message count, i.e., high latency overhead. This work addresses this shortcoming by proposing new fine-grain and medium-grain models that are able to minimize communication volume and message count in a single partitioning phase. The new models utilize message nets in order to encapsulate the minimization of total message count. We further fine-tune these models by proposing delayed addition and thresholding for message nets in order to establish a trade-off between the conflicting objectives of minimizing communication volume and message count. The experiments on an extensive dataset of nearly one thousand matrices show that the proposed models improve the total message count of the original nonzero-based models by up to 27% on the average, which is reflected on the parallel runtime of SpMV as an average reduction of 15% on 512 processors.

Framework for Cross Layer Energy Optimization in Wireless Sensor Networks

Cross-layer routing technique interacts among the various layers of the OSI model and exchanges information among them. It enhances the usage of network resources and achieves significant performance improvements in Quality of Service (QoS) parameters. The Low Energy Adaptive Clustering Hierarchy Protocol (LEACH) routing algorithm consumes higher energy due to communication overhead and thus, a hierarchical model-based routing protocol named Cross-Layer Energy Efficient Scalable-Low Energy Adaptive Clustering Hierarchy Protocol (CLEES-LEACH) is proposed. This increases scalability using the Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) protocol between the intermediary node and cluster head, with the overhead of latency. A Linear Programming model is used, which further makes use of scheduling to overcome latency. Energy efficiency and latency are addressed with the proposed cross-layer routing algorithm CLEESLEACH. The cross-layer design establishes Physical, Media Access Control (MAC), and Network layer interactions in the proposed algorithm. The present LEACH algorithm also increases the network overhead as there is no mechanism for communication among the network layer and consumes high energy. In the proposed algorithm CLEES-LEACH, latency is reduced to 25% and throughput is maximized to 20% compared to existing Energy-Efficient Distributed Schedule Based protocol (EEDS) and Integer Linear Programming (ILP) protocols. The energy consumption is also reduced to 20 % and the scalability is increased to 10 % compared to the existing LEACH and CL-LEACH protocols. These results are shown by using NS3 simulation.

Dandelion++

Recent work has demonstrated significant anonymity vulnerabilities in Bitcoin's networking stack. In particular, the current mechanism for broadcasting Bitcoin transactions allows third-party observers to link transactions to the IP addresses that originated them. This lays the groundwork for low-cost, large-scale deanonymization attacks. In this work, we present \Algopp, a first-principles defense against large-scale deanonymization attacks with near-optimal information-theoretic guarantees. Dandelion++ builds upon a recent proposal called Dandelion that exhibited similar goals. However, in this paper, we highlight some simplifying assumptions made in Dandelion, and show how they can lead to serious deanonymization attacks when violated. In contrast, Dandelion++ defends against stronger adversaries that are allowed to disobey protocol. Dandelion++ is lightweight, scalable, and completely interoperable with the existing Bitcoin network. We evaluate it through experiments on Bitcoin's mainnet (i.e., the live Bitcoin network) to demonstrate its interoperability and low broadcast latency overhead.

Dandelion++

Recent work has demonstrated significant anonymity vulnerabilities in Bitcoin's networking stack. In particular, the current mechanism for broadcasting Bitcoin transactions allows third-party observers to link transactions to the IP addresses that originated them. This lays the groundwork for low-cost, large-scale deanonymization attacks. In this work, we present Dandelion++, a first-principles defense against large-scale deanonymization attacks with near-optimal information-theoretic guarantees. Dandelion++ builds upon a recent proposal called Dandelion that exhibited similar goals. However, in this paper, we highlight some simplifying assumptions made in Dandelion, and show how they can lead to serious deanonymization attacks when violated. In contrast, Dandelion++ defends against stronger adversaries that are allowed to disobey protocol. Dandleion++ is lightweight, scalable, and completely interoperable with the existing Bitcoin network.We evaluate it through experiments on Bitcoin's mainnet (i.e., the live Bitcoin network) to demonstrate its interoperability and low broadcast latency overhead.

PTAT

As the memory access footprints of applications in areas like data analytics increase, the latency overhead of translation lookaside buffer (TLB) misses increases. Thus, the efficiency of TLB becomes increasingly critical for overall system performance. Analyzing TLB miss traces is useful for hardware architecture design and software application optimization. Utilizing cycle-accurate simulators or instrumentation tools is very time-consuming and/or inaccurate for tracing and profiling TLB misses. In this article, we propose an efficient and precise tool to collect and profile last-level TLB misses. This tool utilizes a novel software method called Page Table Access Tracing (PTAT), storing last-level page table entries of certain workload processes into a reserved uncached memory region. Therefore, each last-level TLB miss incurred by user process corresponds to one uncached page table access to main memory, which can be captured and recorded by a hardware memory bus monitor. The detected information is then dumped into offline storage. In this manner, full TLB miss traces are collected and can be analyzed flexibly. Compared to previous software-based methods, this method achieves higher performance. Experiments show that, compared with a state-of-the-art kernel instrumentation method (BadgerTrap), which lacks complete dumping trace function, the speedup is still up to 3.88-fold for memory-intensive benchmarks. Due to the improved efficiency and completeness of tracing, case studies validate that more flexible profiling can be conducted, which is of great significance for TLB performance optimization. The accuracy of PTAT is verified by both dedicated sequence and performance counters.

Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers

The main memory system has become crucial not only because it has to meet an increasing bandwidth requirement, but also because it has to seamlessly support many concurrently executing applications. In order to improve memory performance, a memory controller with efficient arbitration is necessary. It is well known that memory performance is dependent on the memory access patterns. The offline performance analysis has difficulty analyzing the Dynamic Random Access Memory (DRAM) performance accurately because a huge set of trace patterns is needed. This paper proposes a novel profiler that is synthesized with a memory controller in order to monitor and analyze the memory controller performance at runtime. In this paper, five key metrics for performance evaluation are defined and they are monitored and evaluated at runtime by the proposed profiler. A prototype system with a processor core, a memory controller, DRAM modules, and peripheral devices are implemented on a field-programmable gate array (FPGA) board to carry out the experiments. It has been observed that the worst latency overhead differs for each benchmark. In addition, a new overall overhead estimation method is proposed to estimate the memory access latency overhead in time, and this method can be used to evaluate the performance of a certain memory arbitration method depending on running applications.

Encoding Short Ranges in TCAM Without Expansion: Efficient Algorithm and Applications

We present range encoding with no expansion (RENE)— a novel encoding scheme for short ranges on Ternary content addressable memory (TCAM), which, unlike previous solutions, does not impose row expansion , and uses bits proportionally to the maximal range length. We provide theoretical analysis to show that our encoding is the closest to the lower bound of number of bits used. In addition, we show several applications of our technique in the field of packet classification, and also, how the same technique could be used to efficiently solve other hard problems, such as the nearest-neighbor search problem and its variants. We show that using TCAM, one could solve such problems in much higher rates than previously suggested solutions, and outperform known lower bounds in traditional memory models. We show by experiments that the translation process of RENE on switch hardware induces only a negligible 2.5% latency overhead. Our nearest neighbor implementation on a TCAM device provides search rates that are up to four orders of magnitude higher than previous best prior-art solutions.

Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology

In this paper, a novel offset compensated latch-type sense amplifier consisting of hybrid (current & voltage) sensing operation is proposed for SRAMs. The offset compensation circuitry of the proposed sense amplifier includes FET based capacitors and current injection circuitry (CIC) for compensation against VT mismatch of critical transistor pairs. The proposed amplifier does not cause extra overhead in SRAM access latency. The functionality of the proposed tri-gated FinFET sense amplifier in 20 nm technology is verified using 3D TCAD tool and its efficacy against VT variability is tested with the help of HSPICE simulations. Reliability and performance characteristics of the proposed sense amplifier are compared with recently reported capacitor-based offset compensated sense amplifier (OCSA) and the conventional current-latched sense amplifier (CLSA). The proposed sense amplifier achieves 7.58% and 26.38% higher yield compared to OCSA and CLSA, respectively. In this study, the VT mismatch in all critical transistor pairs of the sense amplifier was introduced simultaneously. The proposed amplifier outperforms OCSA and CLSA in the following: (i) 1.11 and 5.02 times higher offset tolerance, (ii) 1.66 and 2.66 times lower bit-line differential voltage (ΔVin) to achieve target yield of 90%, and (iii) 16.84% and 52.94% lower standard deviation in sensing delay during read-0 operation due to higher offset tolerance. Effect of VDD scaling on yield and performance of various sense amplifiers is also evaluated. Under iso-area condition, the proposed sense amplifier exhibits 17.10% higher yield and × 2.55 higher offset tolerance in comparison with CLSA.

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array

In this study, the authors have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. The authors’ analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. They have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.