Large-signal Transistor Model Research Articles

A Combined Broadband Model for GaN HEMTs in Admittance Domain Based on Canonical Piecewise Linear Functions

In this article, a new large-signal transistor model is proposed. The model combines the advantage of both compact modeling and behavioral modeling techniques, resulting in a new modeling methodology. The intrinsic part of the model is based on the black-box poly-harmonic distortion (PHD) framework, which is implemented using the canonical piecewise linear (CPL) functions. Thus, the new intrinsic model can cover a broad operating frequency band, across a wide range of input powers, using a compact set of model parameters. While at each fixed operating frequency and input power, the model can also accurately predict device behavior over the complete Smith chart. For the extrinsic model, the traditional extrinsic parasitic network is used, enabling access to the intrinsic device plane, as required for waveform engineering. This work examines intrinsic admittance domain models implemented using both the linear and quadratic poly-harmonic expansions. An <inline-formula> <tex-math notation="LaTeX">$8 \times 125\,\,\mu \text{m}$ </tex-math></inline-formula> GaN HEMT device with a 0.25-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate feature size and a commercial 10-W GaN HEMT is used during the simulation and experimental model validation. Model implementations show excellent interpolation and extrapolation capability over the frequency band across a range of input power levels in both the frequency domain and the time domain.

Transistor Model Building for a Microwave Power Heterojunction Bipolar Transistor

This article describes the detailed development of a large-signal transistor model for a microwave power heterojunction bipolar transistor (HBT). Based on the neurospace-mapping (Neuro-SM) technique, this model uses neural networks to map a coarse model space represented by the existing model simulations onto the fine model space represented by device measurements. This article tied for first place in the Microwave Transistor Modeling Student Design Competition at the 2014 IEEE International Microwave Symposium (IMS2014) held in Tampa, Florida.

Extraction of a Model for a Microwave Power pHEMT

This article presents the development of a large-signal transistor model for a power microwave pseudomorphic high-electron mobility transistor (pHEMT). This model won the first prize in the Microwave Transistor Modeling student competition held during the 2013 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium (IMS2013) in Seattle, Washington.

A 1–3-GHz Digitally Controlled Dual-RF Input Power-Amplifier Design Based on a Doherty-Outphasing Continuum Analysis

<?Pub Dtl=""?> This paper presents a linear multi-harmonic analysis method to evaluate the performance of digitally controlled dual RF-input power amplifiers (PAs). The method enables, due to its low computational cost, optimization of PA efficiency and bandwidth in a complex design space involving two independent inputs. Under the idealized assumption of short-circuited higher harmonics, the analysis is used to prove the existence of a Doherty-outphasing continuum, featuring high average efficiency over 100% fractional bandwidth. With this result as a foundation, a combiner incorporating microwave transistor parasitics is analyzed without assuming short-circuited higher harmonics, showing that high average efficiencies are also achievable under more realistic conditions. A PA is straightforwardly designed from these calculation results using two 15-W GaN HEMTs. The simulated layout-ready (large-signal transistor model) PA average drain efficiency exceeds 50% over 1.1–3.7 GHz for a 6.7-dB peak-to-average power-ratio WCDMA signal. The measured PA has a maximum output power of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{44}} \pm {\hbox{0.9}}$</tex></formula> dBm and a 6-dB output power back-off (OPBO) power-added efficiency (PAE) of 45% over 1–3 GHz. After applying digital pre-distortion, excellent linearity is demonstrated when transmitting the WCDMA signal, resulting in an adjacent channel leakage power ratio lower than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{\hbox{57}}$</tex></formula> dBc with corresponding average PAE of 50% and 40% at 1.2 and 2.3 GHz, respectively. This is, to the authors' knowledge, the most wideband OPBO efficiency enhanced PA reported to date, proving the effectiveness of employing linear multi-harmonic analysis in dual-input PA design.

Design and model studies for solid-state power amplification at 210 GHz

The high millimeter-wave (mmW) frequency range offers new possibilities for high-resolution imaging and sensing as well as for high data rate wireless communication systems. The use of power amplifiers of such systems boosts the performance in terms of operating range and/or data rate. To date, however, the design of solid-state power amplifiers at frequencies about 210 GHz suffers from limited transistor model accuracy, resulting in significant deviation of simulation and measurement. This causes cost and time consuming re-design iterations, and it obstructs the possibility of design optimization ultimately leading to moderate results. For verification of the small-signal behavior of our in-house large-signal transistor model, S-parameter measurements were taken from DC to 220 GHz on pre-matched transistors. The large-signal behavior of the transistor models was verified by power measurements at 210 GHz. After model modification, based on process control monitor (PCM) measurement data, the large-signal model was found to match the measurements well. A transistor model was designed containing the statistical information of the PCM data. This allows for non-linear spread analysis and reliable load-pull simulations for obtaining the highest available circuit performance. An experimental determination of the most suitable transistor geometry (i.e. number of gate fingers and gate width) and transistor bias was taken on 100 nm gate length metamorphic high electron mobility transistor (mHEMT) transistors. The most suitable combination of number of fingers, gate width and bias for obtaining maximum gain, maximum output power, and maximum power added efficiency (PAE) at a given frequency was determined.

Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model

The improved RF performance of silicon-based technologies over the years and their potential use in telecommunication applications has increased the research in RF modelling of MOS transistors. Especially for analog circuits, accurate RF small signal and large signal transistor models are required. In this paper, we propose an accurate, non-quasi-static, large signal (i.e., nonlinear) RF MOSFET model. Our model consists of a current source and a charge source at the drain terminal and a charge source at the gate terminal. The sources' magnitudes are calculated from the gate-bias and drain-bias dependent elements of the MOSFET equivalent circuit. The MOSFET equivalent circuit elements on itself are extracted from S-parameters at all gate voltages and drain voltages that occur in large signal operation. The accuracy of the equivalent circuit based model is validated by large signal RF measurements using a nonlinear network measurement system. Large signal modelling results using the BSIM3v3 compact model are also presented. Both the equivalent circuit based model and the BSIM3v3 model meet the requirements to describe accurately the RF large signal behaviour of MOS transistors.

A compact physical large-signal model for high-speed bipolar transistors at high current densities&amp;#8212;Part I: One-dimensional model

A compact physical large-signal transistor model is presented that is suited for simulating high-speed bipolar IC's even if the transistors are operated deeply within the high-current region (including quasi-saturation). Like the well-known and currently used Gummel-Poon model, it is based on the integral charge-control relation (ICCR) proposed by Gummel. However, in the high-current region it shows much better accuracy, especially for high-frequency and switching operation. This is mainly a result of the fact that the transit time (and thus the minority-carrier charge) is chosen as a basic model parameter, which is carefully measured and accurately approximated by analytical expressions throughout the total interesting operating range. In Part I of the work, presented here, the model and its parameters are described for the one-dimensional case. Its validity is verified by comparison with exact numerical transistor simulations of both the dc characteristics and the switching behavior. The simulations are based on doping profiles that are typical of transistors in high-speed IC's. Methods for determination of the model parameters are presented. In Part II [1], the model is extended to the two-dimensional case, i.e., to real transistors. It is experimentally verified by measuring the dc characteristics and the switching behavior of very fast transistors with high transit frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ≈ 7 GHz) and small emitter stripe width. The complete model, which is called HICUM (from "high-current model"), was already implemented in the circuit analysis program SPICE 2.

A Modified Ebers-Moll Transistor Model for RF-Interference Analysis

This paper develops analytical techniques for the study of nonlinear RF and microwave effects in semiconductor devices. Rectification in p-n junctions is discussed, and a novel large-signal transistor model is developed, based upon modifications to standard Ebers-Moll formulations for bipolar transistors. Use of the models in worst-case analysis is discussed, with ranges of parameters given based on a simplified analysis of rectification in ideal diodes.

Erratum: Improving the large-signal models of bipolar transistors by dividing the intrinsic base into two lateral sections

In large-signal transistor models, the lateral voltage drop across the base region is usually represented by a single-lump constant base spreading resistance. The letter demonstrates, for the switching mode, that a much better approximation of the 2-dimensional transistor can already be achieved by dividing the intrinsic base into merely two sections (2-section model).

Improving the large-signal models of bipolar transistors by dividing the intrinsic base into two lateral sections

In large-signal transistor models, the lateral voltage drop across the base region is usually represented by a single-lump constant base spreading resistance. The letter demonstrates, for the switching mode, that a much better approximation of the 2-dimensional transistor can already be achieved by dividing the intrinsic base into merely two sections (2-section model).

Design of Self-Limiting Transistor Sine-Wave Oscillators

By combining the describing function approach with a large signal transistor model and certain simplifying assumptions, it has been possible to develop a set of universal curves yielding selflimiting operating amplitudes for a large class of transistor sinewave oscillators. The variable parameter in this presentation is the dc voltage drop across the emitter bias resistor in the circuit with oscillations absent. Since this parameter may be easily calculated, the material presented allows the design of oscillators for any allowable operating amplitude. In a companion paper the method is extended to include collector saturation limiting and calculations of the onset of squegging.

Circuit Models to Predict Switching Performance of Nanosecond Blocking Oscillators

This paper presents circuit models for calculating the switching time of transistor blocking oscillators operating in the nanosecond time domain. The accuracy of the original theory proposed by Linvill and Mattson is tested using transistors with increasing alpha cutoff frequency. It is found that this theory gives close correlation between measured and calculated switching time for low-frequency transistors; however, for high-frequency units, differences as large as an order of magnitude exist. A new model is presented which adequately describes the oscillator performance with high-frequency transistors. Although large signals are involved in the circuit's operation, a large-signal transistor model is necessary only during a description of initial turnon. Switching time minimization is studied using the new models by examining the sensitivity of the oscillator switching time to variation in circuit model parameters. Graphs which show theoretical and measured sensitivity to parameter variation are presented. Three blocking oscillators have been constructed and tested to experimentally verify the accuracy of the new models. Measured results demonstrate that the equations derived from the new circuit models are quite adequate for calculating switching times of blocking oscillators in the nanosecond region.

Transient Analysis and Device Characterization of ACP Circuits

Characterization of devices for high speed ACP (Advanced Circuit Program) circuits demands an accurate study of transients and switching delays. This paper describes (a) the large-signal transistor model evolved for the purpose of carrying out such an analysis; (b) methods of measuring device parameters with relevant theory; (c) computational techniques most adaptable; and (d) correlation between predicted and observed transients. Many new ideas in the development of the device model, measurements, and computational procedure are reported and could be used for any general circuit analysis.