Large-scale Interconnect Research Articles

Long-term effects of soft-chromising Ni-electroplated AISI 441 commodity steel for SOC stack interconnects

Using commodity steel AISI 441 with Ni-based oxide coatings can facilitate large-scale interconnect manufacturing for solid oxide cell stacks, but adverse Ni-diffusion limits the high-temperature suitability. As a remedy, chromium is here added to the steel by a soft-chromising treatment. The (cyclic) oxidation resistance of virgin and soft-chromised AISI 441 is evaluated up to 8300 h at 780 °C, and further benchmarked against more commonly used Crofer 22 APU, with a Co(Mn)-spinel coating. Results revealed lowest isothermal oxidation kinetics for the soft-chromised, Ni-coated AISI 441, further preventing oxide spallation otherwise observed during thermal cycling of the virgin AISI 441 counterpart.

Enhancing high-temperature suitability of Ni-electroplated AISI 441 steel by soft-chromising

Commodity ferritic steel AISI 441, electroplated with nickel, can improve large-scale interconnect manufacturing for solid oxide cell stacks, but nickel-diffusion-induced chromium depletion in the steel surface adversely affects the oxidation behaviour. The present study explores soft-chromising to limit oxidation in Ni-coated AISI 441 during a simulated stack sealing exposure. Complementary in-situ X-ray diffraction and ex-situ electron microscopy revealed that soft-chromising favours the formation of protective external Cr(Mn)-rich oxide and lowers detrimental internal oxidation. Soft-chromising seems promising for the development of new low-cost commodity steels that allow nickel in protective coatings, thereby facilitating an interconnect design appropriate for large-scale production.

Optical interconnects for extreme scale computing systems

Face-to-face comparison of major large scale HPC interconnects.Review of challenges and solutions for increased use of optics in HPC.Description of optical switching, in terms of principle, limitations, technical requirements and benefits. Large-scale high performance computing is permeating nearly every corner of modern applications spanning from scientific research and business operations, to medical diagnostics, and national security. All these communities rely on computer systems to process vast volumes of data quickly and efficiently, yet progress toward increased computing power has experienced a slowdown in the last number of years. The sheer cost and scale, stemming from the need for extreme parallelism, are among the reasons behind this stall. In particular, very large-scale, ultra-high bandwidth interconnects, essential for maintaining computation performance, represent an increasing portion of the total cost budget.Photonic systems are often cited as ways to break through the energy-bandwidth limitations of conventional electrical wires toward drastically improving interconnect performance. This paper presents an overview of the challenges associated with large-scale interconnects, and reviews how photonic technologies can contribute to addressing these challenges. We review some important aspects of photonics that should not be underestimated in order to truly reap the benefits of cost and power reduction.

Hi-LION: Hierarchical Large-Scale Interconnection Optical Network With AWGRs [Invited

This paper proposes Hi-LION, a hierarchical large-scale interconnect optical network, exploiting high-radix arrayed waveguide grating routers (AWGRs) in hierarchy to achieve very large scale and low latency interconnection of many computing nodes. By using the unique wavelength routing property of AWGRs together with electrical switching inside the processors, Hi-LION can scale beyond 100,000 nodes. A comparison with a legacy fat-tree network with a 3:1 oversubscription ratio shows that Hi-LION can achieve 2.5-fold throughput increases while using less than 20% of the global switches and cables.

Fast ${\cal H}$-Matrix-Based Direct Integral Equation Solver With Reduced Computational Cost for Large-Scale Interconnect Extraction

In this paper, we propose a fast H-matrix-based direct solution with a significantly reduced computational cost for an integral-equation-based capacitance extraction of large-scale 3-D interconnects in multiple dielectrics. We reduce the computational cost of an H-matrix-based computation by simultaneously optimizing the H-matrix partition to minimize the number of matrix blocks and minimizing the rank of each matrix block based on a prescribed accuracy. With the proposed cost-reduction method, we develop a fast LU-based direct solver. This solver possesses a complexity of kCspO (NlogN) in storage, a complexity of k2Csp2O(Nlog2N) in LU factorization, and a complexity of kCspO(NlogN) in LU solution, where k is the maximal rank, Csp is a constant dependent on matrix partition, and the constant kCsp is minimized based on accuracy by the proposed cost-reduction method. The proposed solver successfully factorizes dense matrices that involve millions of unknowns in fast CPU time and modest memory consumption, and with the prescribed accuracy satisfied. As an algebraic method, the underlying fast technique is kernel independent.

A novel interconnect-optimal power model considering self-heating effect

Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, in which a non-uniform interconnection structure is adopted. This model takes into account the self-heating effect and is constrained by delay, bandwidth, area, minimum interconnect width and minimum interconnect space. The validity of the proposed model is verified by 90 nm and 65 nm complementary metal-oxide semiconductor technology. The results indicate that the proposed model can cause a power consumption reduction as high as 35%, and yet the delay, area, and bandwidth are not deteriorated, when compared with the conventional power model. The proposed optimal model can be used for designing large scale interconnect router and clock network in network-on-chip structure.

Compressed Passive Macromodeling

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed technique.

Scalability Analysis of Optical Intrasystem Interconnects

Architecture of network elements such as large routers and switches is becoming more and more complex due to the constantly increasing requirements on both capacity and performance. Already today, high-performance routers having capacities of more than several Tb/s can not be packaged in a single rack of equipment. Complex and spatially distributed multirack routers comprising a large number of line cards, switching modules and high-speed ports have already become reality. A consequence of this trend is that internal interconnecting system also becomes large and complex. Interconnection distances, total number of cables and power consumption increase rapidly with the increase in capacity, which can cause limitations in scalability of the whole system. This paper addresses requirements and limitations of large-scale optical interconnects. Various point-to-point interconnects and two optically switched interconnection options were studied with regard to their scalability by considering various impairments on optical signal, required number of fiber links and power consumption. Results of this study are presented and discussed in this paper.

ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction

Parasitic extraction is one of the key techniques in very large scale integration design that has been widely used to build the equivalent-circuit model of interconnects. In this paper, a parallel adaptive finite-element method (AFEM) for capacitance extraction of large-scale interconnects (ParAFEMCap) is developed to provide extremely high parallel scalability and numerical accuracy. First, the proposed ParAFEMCap has the potential of high parallel scalability by taking advantages of several advanced parallel techniques, such as parallel adaptive mesh refinement and dynamic load balancing. To the best of the authors' knowledge, this is the first capacitance extraction field solver that is able to run in parallel on hundreds and even thousands of CPU cores. Second, the proposed ParAFEMCap is based on the AFEM, which is proven to converge to the exact solution of the electromagnetic problems in a theoretically quasi-optimal rate. The solution precision of ParAFEMCap can easily be controlled by varying the threshold for the a posteriori error estimator, while the computational time can easily be reduced by increasing the number of CPU cores. Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral-equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems. Numerical experiments will demonstrate that ParAFEMCap has the advantages of high computational efficiency and accuracy for solving the capacitance extraction problem of large-scale interconnects with complex multilayer structures.

An LU Decomposition Based Direct Integral Equation Solver of Linear Complexity and Higher-Order Accuracy for Large-Scale Interconnect Extraction

A fast LU factorization of linear complexity is developed to directly solve a dense system of linear equations for the capacitance extraction of any arbitrary shaped 3-D structure embedded in inhomogeneous materials. In addition, a higher-order scheme is developed to achieve any higher-order accuracy for the proposed fast solver without sacrificing its linear computational complexity. The proposed solver successfully factorizes dense matrices that involve more than one million unknowns in fast CPU run time and modest memory consumption. Comparisons with state-of-the-art integral-equation-based capacitance solvers have demonstrated its clear advantages. In addition to capacitance extraction, the proposed LU solver has been successfully applied to large-scale full-wave extraction.

A novel temperature-aware distributed interconnect power model

Base on the lumped resistance-capacitance （RC） tree power model，a novel distributed interconnect dynamic power analytical model was proposed，which considers the effect of non-uniform temperature distribution along the interconnect. The new model overtakes the defect that the lumped model cannot represent the effect of non-uniform temperature distribution on the resistance of interconnect，and estimates the total power consumption of RC tree under a non-ideal unit step input. The proposed model is used to calculate the total power consumption of interconnect under nanometer-scale complementary metal-oxide semiconductor （CMOS） typical process. The results show that the longer the interconnected line is，the greater the effect of non-uniform temperature distribution on the power consumption is，and the dynamic power per unit length keeps constant under different processes. The proposed model can accurately calculate the dynamic power of interconnects，thus can be used to optimize design of large scale interconnect router and clock network in network-on-chip structure.

Full-Wave Analysis of Large-Scale Interconnects Using the Multilevel UV Method With the Sparse Matrix Iterative Approach (SMIA)

Moving towards the goal of analyzing whole printed circuit boards (PCBs) and packages using full-wave electromagnetic (EM) methods, the multilevel UV method is applied to the method-of-moments (MoM) solution of the current on large-scale interconnects. The MoM solution uses the layered media Green's functions computed using the numerical modified steepest-descent path (NMSP) method, and is applied to the exterior layers of the interconnect structure. The sparse matrix iterative approach (SMIA) is used to speed up the solution of the iterative matrix solver. The iterative solver is also accelerated by using larger blocks in the block diagonal inverse preconditioner. With the multilevel UV method, a fast solution is presented for solving the current on large-scale interconnects on thin layered structures at high frequencies. We show an example of an interconnect structure that has horizontal dimensions of 12.675 lambda t 12.876 lambda with 24\thinspace 848 current unknowns and an interconnect fractional area of approximately 31%. This problem takes a total of 21 min 20 s to solve for the current on the traces on a Pentium 3.2-GHz CPU with 4 GB of RAM.

TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits

In this paper, a novel method to efficiently reduce the terminal number of general linear-interconnect circuits with a large number of input or output terminals considering delay uncertainty is proposed. Our new algorithm is motivated by the fact that terminal reduction can lead to a more compact order-reduced model and the observation that very large-scale integration interconnect circuits have many similar terminals in terms of their timing and delay metrics due to their closeness in structure or due to the mathematical discretization using meshing in finite-difference or finite-element scheme during the extraction process. The new method, called TermMerg ( Proc. ICCAD, p. 821, 2005), is based on the moments of the circuits as the metrics for the timing or delay. It then employs a singular-value-decomposition (SVD) method to determine the best number of clusters based on the low-rank approximation. After this, the -means clustering algorithm is used to cluster the moments of the terminals into the different clusters. The proposed method can work with any passive-model order reduction and ensure the passive models. In contrast, we show that singular value decomposition model order reduction (SVDMOR) does not generate passive models in general. Passivity enforcement in SVDMOR will significantly hamper the terminal-reduction effectiveness. Experimental results on a number of real industry interconnect circuits demonstrate the effectiveness of the proposed method and show also that the proposed method is more accurate than SVDMOR when the used moment matrix does not give good terminal correlations.

A reduction technique of large‐scale RCG interconnects in the complex frequency domain

AbstractHigh‐speed digital LSI chips usually consist of many sub‐circuits coupled with multi‐conductor interconnects embedded in the substrate. They sometimes cause serious problems of the fault switching operations due to the time‐delays, crosstalks, reflections, etc. In order to solve these problems, it is very important to develop a user‐friendly simulator for the analysis of LSIs coupled with interconnects. In this paper, we consider a large‐scale gate‐array circuit coupled with multi‐conductor RCG interconnects. At first, we propose a new method for calculating the dominant poles of the impedance matrix, which give the large effects to the transient response. The corresponding residues are estimated by the least squares method. Using these poles and residues, the input–output relation of each interconnect can be described by the partial fractions. After then, the interconnect is replaced by the equivalent circuit realizing the partial fractions. In this way, we can easily develop a user‐friendly simulator familiar with SPICE. We found from many examples that the good results can be obtained using only few dominant poles around the origin. Furthermore, the reduction ratio of our method is very large especially for large scale interconnects. Copyright © 2004 John Wiley & Sons, Ltd.

Influence of crosstalk on the scalability of large OTDM interconnects using a novel rapidly reconfigurable highly scalable time-slot tuner

We studied the coherent crosstalk properties of a novel time-slot tuner and its implications on the scalability of large-scale OTDM interconnects. A statistical model for the coherent crosstalk was used to evaluate the performance degradation which arises from the coherent interference between signal and crosstalk fields. Based upon this highly scalable, rapidly tunable channel selector, large all-optical TDM switching interconnects up to 100 nodes with an aggregate bandwidth of hundreds of Gb/s can be feasible, using off-the shelf electro optical (E/O) modulators with on/off extinction ratios of 30 dB. The results show the potential to further scale the size of the system up to hundreds of nodes, given on/off extinction ratios of 35-40 dB for the modulators.

Large Scale Interconnects for Aerospace Applications

This paper addresses three main technologies of large scale interconnects that have been evaluated at the Microelectronics Department of Crouzet Aerospace for chip and wire or LCCCs (Leadless Ceramic Chip Carriers). The P/I (Packaging and Interconnect) structures that will be discussed are either ceramic multilayer with MLTF multilayer thick film, and CMC (Cofired Multilayer Ceramic) or advanced PWBs. The paper will present the R&D that has been carried out on MLTF and advanced PWBs and the evaluation programme now in progress for CMC. Test results are given, technology status and next generation interconnects are described and some aerospace applications are presented.

A means of reducing custom LSI interconnection requirements

Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective circuits that naturally occur on such large circuit arrays, it has been necessary to customize each wafer's interconnection mask to its unique yield pattern. The authors examine in detail a means of using each mask set for perhaps several unique wafers, thus providing important custom routing and mask generation cost savings. In the case of pad relocation, only a single mask then comprises the entire custom mask set for several wafer arrays.