A reduction technique of large‐scale RCG interconnects in the complex frequency domain

Abstract

AbstractHigh‐speed digital LSI chips usually consist of many sub‐circuits coupled with multi‐conductor interconnects embedded in the substrate. They sometimes cause serious problems of the fault switching operations due to the time‐delays, crosstalks, reflections, etc. In order to solve these problems, it is very important to develop a user‐friendly simulator for the analysis of LSIs coupled with interconnects. In this paper, we consider a large‐scale gate‐array circuit coupled with multi‐conductor RCG interconnects. At first, we propose a new method for calculating the dominant poles of the impedance matrix, which give the large effects to the transient response. The corresponding residues are estimated by the least squares method. Using these poles and residues, the input–output relation of each interconnect can be described by the partial fractions. After then, the interconnect is replaced by the equivalent circuit realizing the partial fractions. In this way, we can easily develop a user‐friendly simulator familiar with SPICE. We found from many examples that the good results can be obtained using only few dominant poles around the origin. Furthermore, the reduction ratio of our method is very large especially for large scale interconnects. Copyright © 2004 John Wiley & Sons, Ltd.