Large Scale Integration Interconnects Research Articles

Numerical investigation of graphene-silica-silver based VLSI interconnects with tunable multiband infrared absorber for 3D integrated circuits

We propose the multilayer silver-silica-graphene-based very large-scale integration interconnects assisted by a tunable perfect absorption structure over the infrared frequency spectrum of the third window of the optical communication for three-dimensional (3D) integrated circuits (ICs). This absorber is numerically investigated for the different cylindrical silver resonator-based squared geometries. The overall structure is investigated for the wavelength range of 1.4 to 1.6 μm over the infrared spectrum. The adjustable behavior of the absorption spectrum is observed when this structure is studied for various chemical potentials of the graphene sheet. We also present the electric and magnetic field intensity for the nearly perfect absorption conditions to identify the effect of energy concentration over different pixel structures and wavelengths. We also showcased the possible fabrication process for the proposed numerical investigation analysis. Resonator height and width have also been simulated numerically to find the resonance shift in the absorber. The adaptable behavior of the suggested structure has potential applications in a wide range of scientific fields, including biosensors, solar absorbers, optical communication, and the fabrication of 3D ICs. Simulations are performed using the COMSOL Multiphysics software module

Fabrication of carbon nanomaterials using supercritical states of ethanol and binary system of ethanol and carbon dioxide for LSI interconnects

The fabrication and filling of carbon nanomaterials (CNMs) into nanoholes and trenches using supercritical method were achieved for the first time at substrate temperatures of 500–700 °C and pressures of 10–20 MPa. Two supercritical fluid systems were examined: (1) ethanol and carbon dioxide were used as the carbon source and supercritical fluid, respectively, and (2) ethanol was used as both the carbon source and supercritical fluid. Multiwalled carbon nanotubes with diameters of 8–20 nm were also confirmed to be formed. The present work introduces a new technique of preparing CNMs for application as large-scale integration interconnects.

SD-PUF: Spliced Digital Physical Unclonable Function

Digital circuit physical unclonable function (PUF) has been attracting attentions for the merits of resilience to the environmental and operational variations that analog PUFs suffer from. Existing state-of-the-art digital circuit PUFs, however, are either hybrid of analog-digital circuits which are still under the shadow of vulnerability, or impractical for real-world applications. In this paper, we propose a novel highly nonlinear and secure digital PUF (D-PUF) and the spliced version SD-PUF. The fingerprints are extracted from intentionally induced very large-scale integration interconnect randomness during lithography process, as well as a post-silicon shuffling process. Strongly skewed CMOS latches are used to ensure the immunity against environmental and operational variations. Crucially, a highly nonlinear logic network is proposed to effectively spread and augment any subtle interconnect randomness, which also enables strong resilience against machine learning attacks. On top of it, the expandable architecture of the proposed logic network empowers a novel post-silicon shuffle-splice mechanism, where multiple randomly selected D-PUFs are spliced to be one SD-PUF, pushing the statistical security to a much higher level, while significantly reducing the mask cost per PUF device. It also decouples the trustworthy demands enforced to the foundries or other third party manufacturers. Our proposed PUFs demonstrate close to ideal performance in terms of statistical metrics, including 0 intra-Hamming distance. Various state-of-the-art machine learning models show prediction accuracies almost no better than random guesses when attacking to the proposed PUFs. We also mathematically prove the probability of existence of identical SD-PUF pair is significantly lower than that of D-PUF pair, e.g., such probability of an SD-PUF spliced by 30 D-PUFs is ${2.3\times 10^{-22}}$ , which is 19 order magnitude lower than that of D-PUF. Benefited from the proposed shuffle-splice mechanism, the mask cost per SD-PUF is also reduced by ${300\times }$ than that of D-PUF.

An Unconditionally Stable FDTD Model for Crosstalk Analysis of VLSI Interconnects

In this paper, an unconditionally stable finite-difference time-domain (US-FDTD) model is proposed for the crosstalk noise analysis of coupled very large scale integration interconnects. The accuracy of the proposed model is validated against the conventional FDTD model and HSPICE. It is observed that the proposed model is as accurate as the conventional FDTD and HSPICE. It is also observed that the stability of the proposed model is not constrained by the Courant–Friedrichs–Lewy stability condition. Depending on the time-step size, the proposed model can be up to $100\times $ faster than the conventional FDTD.

High-Frequency Behavioral Multiconductor Cable Modeling for EMI Simulations in Power Electronics

Computationally efficient high-frequency circuit models of long cables are necessary for accurate analysis of electromagnetic interference in power converter systems. A methodology for behavioral modeling of multiconductor power cables based on measurements is presented in this paper. The procedure is founded on and extended from the techniques developed and used for modeling very large scale integration interconnects and printed circuit board transmission lines in packaging and microwave engineering. The methodology accurately captures the frequency-dependent behavior in the conductive emission range, including dc, using a vector-fitting rational-function approximation and results in stable, causal, and passive equivalent circuits. The models are validated by comparing the results obtained using simulations with the measurements in both frequency and time domain.

Experimental and numerical evaluation of interfacial adhesion on Cu/SiN in LSI interconnect structures

The local interfacial strength is a key factor in designing and fabricating advanced three-dimensional large-scale integration interconnect structures. In this paper, both local fracture tests and three-dimensional elastic–plastic crack propagation analysis for a 10μm×10μm specimen were performed, and the local interfacial adhesion between a Cu interconnect and a SiN cap layer were evaluated. The three-dimensional elastic–plastic crack propagation simulation was developed to evaluate the interfacial adhesion that eliminated the effect of progressive plastic dissipation energy during crack propagation. The results show that the average interfacial adhesion for Cu/SiN is 4.46±0.17J/m2. The crack propagation behavior and fracture pattern depend on the interfacial adhesion, and these differences are due to the plastic yielding of the side edge of the specimen. The critical interfacial adhesion for the onset of shear fracture is 4.92J/m2, which is the upper bound of the interfacial adhesion evaluation for the 10μm×10μm specimen.

Compact and Accurate Models of Large Single-Wall Carbon-Nanotube Interconnects

Single-wall carbon nanotubes (SWCNTs) have been proposed for very large scale integration interconnect applications and their modeling is carried out using the multiconductor transmission line (MTL) formulation. Their time-domain analysis has some simulation issues related to the high number of SWCNTs within each bundle, which results in a highly complex model and loss of accuracy in the case of long interconnects. In recent years, several techniques have been proposed to reduce the complexity of the model whose accuracy decreases as the interconnection length increases. This paper presents a rigorous new technique to generate accurate reduced-order models of large SWCNT interconnects. The frequency response of the MTL is computed by using the spectral form of the dyadic Green's function of the 1-D propagation problem and the model complexity is reduced using rational-model identification techniques. The proposed approach is validated by numerical results involving hundreds of SWCNTs, which confirm its capability of reducing the complexity of the model, while preserving accuracy over a wide frequency range.

Characteristics of Al substituted nanowires fabricated by self-aligned growth for future large scale integration interconnects

Substituted Al nanowires for use in future large scale integration interconnects were fabricated by self-aligned growth. The resistivity of an Al substituted nanowire 80 nm in width, 100 nm in height, and 20 μm in length was 4.7 μΩ cm, which is 48% lower than that of an Al nanowire with the same dimensions fabricated using a bottom-up approach. The variation in the resistivity was in a narrow range (14%) over a Si wafer. The TEM imaging revealed that the Al substituted nanowire had a bamboo-like structure with grains larger than 1.6 μm. The electromigration activation energy was 0.72 eV, which is comparable to that of a pure Al wire with a bamboo-like structure. The product of the critical current density and wire length was 1.3 × 103 A/cm at 250 °C; 2.1 times higher than that of a pure Al wire with a polycrystalline structure. The acceleration of electromigration due to current density was 2.0, indicating that incubation time dominates electromigration lifetime. The prolonged incubation time observed in the electromigration test is attributed to the reduction in electromigration-induced mass transport due to the microstructure of the Al substituted nanowire. Even the formation of a small void immediately after incubation may be a fatal defect for nanoscale Al wires.

Carbon nanotubes for next generation very large scale integration interconnects

We investigated the application of one-dimensional fluid model in modeling of electron transport in carbon nanotubes and equivalent circuits for interconnections and compared the performances with the currently used copper interconnects in very-large-scale integration (VLSI) circuits. In this model, electron transport in carbon nanotubes is regarded as quasi one-dimensional fluid with strong electron-electron interaction. Verilog-AMS in Cadence/Spectre was used in simulation studies. Carbon nanotubes of the types single-walled, multiwalled and bundles were considered for ballistic transport region, local and global interconnections. Study of the S-parameters showed higher transmission efficiency and lower reflection losses. Theoretical modeling and computer-aided simulation studies through a complimentary CNT-FET inverter pair, interconnected through a wire, exhibited reduced delays and power dissipations for carbon nanotube interconnects in comparison to copper interconnects in 22 nm and lower technology nodes. The performance of CNT interconnects was shown to be further improved with increase in number of metallic carbon nanotubes. Our study suggests the replacement of copper interconnect with the multiwalled and bundles of single-walled carbon nanotubes for the sub-nanometer CMOS technologies.

TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits

In this paper, a novel method to efficiently reduce the terminal number of general linear-interconnect circuits with a large number of input or output terminals considering delay uncertainty is proposed. Our new algorithm is motivated by the fact that terminal reduction can lead to a more compact order-reduced model and the observation that very large-scale integration interconnect circuits have many similar terminals in terms of their timing and delay metrics due to their closeness in structure or due to the mathematical discretization using meshing in finite-difference or finite-element scheme during the extraction process. The new method, called TermMerg ( Proc. ICCAD, p. 821, 2005), is based on the moments of the circuits as the metrics for the timing or delay. It then employs a singular-value-decomposition (SVD) method to determine the best number of clusters based on the low-rank approximation. After this, the -means clustering algorithm is used to cluster the moments of the terminals into the different clusters. The proposed method can work with any passive-model order reduction and ensure the passive models. In contrast, we show that singular value decomposition model order reduction (SVDMOR) does not generate passive models in general. Passivity enforcement in SVDMOR will significantly hamper the terminal-reduction effectiveness. Experimental results on a number of real industry interconnect circuits demonstrate the effectiveness of the proposed method and show also that the proposed method is more accurate than SVDMOR when the used moment matrix does not give good terminal correlations.

Expression of Concern: Performance Implications of Inductive Effects for Carbon-Nanotube Bundle Interconnect

In this letter, we investigate the impact of inductance on bundles of single-walled carbon nanotubes (SWCNT) for future very large scale integration interconnect applications. Leveraging a scalable equivalent circuit model, we assess the relative impact of magnetic inductance and the worst case theoretical value of kinetic inductance on both delay and voltage overshoot. Based on our results, even if the worst case theoretical value for kinetic inductance is assumed, it will only increase the delay and the voltage overshoot by a maximum of 6% and 3%, respectively. Therefore, kinetic inductance will not be a significant factor in the future SWCNT bundle-based interconnect solutions

Process design of Cu(Sn) alloy deposition for highly reliable ultra large-scale integration interconnects

Cu(Sn) alloys were studied as possible candidates for highly reliable interconnects. For conformational deposition of Cu(Sn) alloy seed layer, the effect of Sn doping and the deposition sequence of Cu(Sn) alloy on Cu wettability were investigated by evaluating the agglomeration behavior of Cu(Sn) seed layers on a TaN barrier. Two different sputter-deposited stacked layers were studied; Cu/Sn/TaN/SiO 2/Si and Sn/Cu/TaN/SiO 2/Si structure. Cu(Sn) alloy layers with 5 at.% Sn were agglomerated more than a pure Cu layer due to the lower melting point of Cu by Sn doping. The agglomeration behavior depended on the deposition sequence; Cu/Sn/TaN/SiO 2/Si structure was agglomerated more than Sn/Cu/TaN/SiO 2/Si structure because Cu atoms on liquid Sn layer can diffuse easily. Consequently, for continuous, thin seed-layer deposition, Sn atoms as an alloy element should be deposited after a continuous Cu layer is formed.

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

Optimization of throughput performance for low-power VLSI interconnects

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance.

Rapid Method to Account for Process Variation in Full-Chip Capacitance Extraction

Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacitances are strictly valid only for the nominal interconnect dimensions; the networked nature of capacitive relationships in dense, complex interconnect structures precludes simple extrapolations of capacitance with dimensional changes. However, the derivatives, with respect to linewidth variation of the analytical models, can be accumulated along with the capacitance itself for each interacting pair of nodes. A numerically computed derivative with respect to metal and dielectric layer thickness variation can also be accumulated. Each node pair's extracted capacitance and its gradient with respect to linewidth and thickness variation on each metal and dielectric layer can be stored in a file. Thus, instead of storing a scalar value for each extracted capacitance, a vector of 3I+1 values will be stored for capacitance and its gradient, where I is the number of metal layers. Subsequently, this gradient information can be used during circuit simulation in conjunction with any arbitrary vector of interconnect process variations to perform sensitivity analysis of circuit performance.

Preconditioned multi-zone boundary element analysis for fast 3D electric simulation

For fast 3D electric simulation, the multi-zone collocation boundary element analysis (BEA) with iterative solver like GMRES algorithm is required. In this paper, we present a scheme of equation assembly with ordering unknowns and collocation points, and a matrix storing structure. A group of easily computed preconditioners based on the mesh neighbor method are then proposed to remarkably quicken the convergence of GMRES iteration, and demonstrate at least 30% time reduction than using the diagonal preconditioner. Compared with the equation assembly in Merkel et al. [Engng Anal Bound Elem 22 (1998) 183], where two unknowns on same interfacial node are arranged subsequently, and two storing schemes in Li et al. and Araujo et al. [Sys Engng Electron 21 (1999) 10; J Chin Inst Engrs 23 (2000) 269], the proposed method generates fewest non-zero blocks and facilitates the matrix–vector multiplication remarkably. Numerical experiments verify the analysis and show a fast iterative multi-zone BEA simulator for actual very large-scale integration interconnects with a large amount of zones.

Buffer insertion with adaptive blockage avoidance

Buffer insertion is a fundamental technology for very large scale integration interconnect optimization. This work presents the repeater insertion with adaptive tree adjustment (RIATA) heuristic that directly extends van Ginneken's classic algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment adapts to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. RIATA can be combined with any performance-driven Steiner tree algorithm and permits various solution search schemes to achieve different solution quality and runtime tradeoffs. Experiments on several large nets confirms that high-quality solutions can be obtained through this technique with greater efficiency than simultaneous approaches.

Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM

A quasi-multiple medium (QMM) method based on the direct boundary element method (BEM) is presented to extract the capacitance of three-dimensional (3-D) very large scale integration interconnects with multiple dielectrics. QMM decomposes each dielectric layer into a few fictitious medium blocks, and generates an overall coefficient matrix with high sparsity. With the storage technique of a sparse blocked matrix and iterative equation solver generalized minimal residual, the QMM can greatly reduce the CPU time and memory usage of large-scale direct BEM computation. Numerical examples of 3-D multilayered and multiconductor structures cut from actual layout show the efficiency of the QMM method for capacitance extraction. We also compared the QMM accelerated BEM with geometry independent measured equation of invariance (GIMEI) and Zhu's overlapping domain decomposition method (ODDM).

A traveling-wave-based waveform approximation technique for the timing verification of single transmission lines

Today's high-speed very large scale integration interconnects are becoming inductively dominated (moderate Q) resistance-inductance-capacitance (RLC) transmission lines. The time-domain system responses of RLC interconnect lines driving load capacitances cannot be accurately represented by using a finite number of poles with exception for a particular case of RC-time-constant-dominant (low Q) RLC systems. In this paper, a new traveling-wave-based waveform approximation technique is presented. The method suggests that a steady-state traveling wave is approximately determined by a three-pole approximation technique. Then the time-domain response of the system can be accurately determined by using the traveling waves that are modeled by multiple reflections. The signal delay models of the RLC interconnect lines are derived as a closed form. The technique is verified by varying the source resistance, load impedance, and transmission line circuit model parameters of several RLC lines. The results show excellent agreement with HSPICE simulation results. That is, approximately 5% error in a 50% delay calculation can be achieved.

Numerical simulation of current crowding phenomena and their effects on electromigration in very large scale integration interconnects

Two types of current crowding structures were simulated in this work. In each structure, both the pattern of current crowding and the magnitude of the associated current density gradient were examined. Factors like line width, curvature, and conductivity, which affect the crowding behavior, were analyzed. The numerical magnitude of the gradient, which changes to a driving force when a potential in the gradient is defined, was found to be high enough to affect the atomic rearrangement during electromigration. It induces void formation in the low current density region of an interconnect, and it causes precipitates to link together rather than to ripen in a two-phase alloy. Also, we found that as the line width scales down, the effects of current crowding become more and more significant.