Large Scale Integrated Circuit Design Research Articles

Chiplets for Integration of Electronic Systems

Scaling down of transistor sizes has made it possible to integrate billions of devices in the same chip, allowing us to build entire electronic systems into tiny “systems on chip” (SoC). For about four decades after the proclamation of Moore's law, device scaling resulted in improvements in area, performance as well as power. In the last two decades, many semiconductor manufacturers stopped investing in new technology nodes since the design, manufacturing, and test challenges in deep submicron technologies are far too steep. Today, semiconductor companies do not rely on improvements in photolithography alone to build more complex systems. Similarly, optimizations at gate level or register-transfer level through electronic design automation tools will not suffice to bring in order-of-magnitude increase in the complexity of SoC, since these tools are already mature. Therefore, optimization at the system level is the only logical step forward. Chiplets represent a system-level packaging innovation and there is much research and development in using this technology for building high-performance computing systems. We believe that it will be worthwhile to include the topic of system-level integration in a course on Very Large-Scale Integrated Circuit Design taught in the Universities and provide a tutorial treatment to help teachers and students.

Ferris-wheel-assisted parylene-C dielectric deposition for improving organic thin-film transistor uniformity

Organic thin film transistor is one of the most promising electronic device technologies for flexible and printed electronics, but device uniformity remains a challenge for large-scale integration circuit design. Despite the advances in semiconductor layers, the quality of dielectric layers is equally important. Parylene-C dielectric has good intrasample thickness uniformity, but demonstrates significant variation among samples fabricated at the same time, thus causing device non-uniformity. In this study, we present a two-dimensional (2D) sample rotation method using a Ferris wheel to improve the thickness uniformity of parylene-C dielectrics. The Ferris wheel averages the deposition rate of parylene-C dielectric on different samples over an identical spherical space, rather than over different horizontal planes by the conventional one-dimensional sample rotation with a rack. The dielectrics fabricated on different cabins of the Ferris wheel demonstrate better thickness uniformity than those fabricated on different floors of the rack, and thus better uniformity of transistors. Specifically, using the 2D rotation Ferris wheel, the coefficient of variation of dielectric thickness is lowered to 0.01 from 0.12 (which uses the conventional rack); the coefficients of variation for the on-state drain current, process transconductance parameter, and threshold voltage of the fabricated transistors are improved to 0.15, 0.16 and 0.08, from 0.33, 0.20 and 0.14, respectively. The improved device uniformity has the potential in complicated flexible circuit design for advanced applications such as edge intelligence.

Forty five nm CMOS low power multilevel active feedback transimpedance amplifier for optical receivers

PurposeRecent advancements in the domain of smart communication systems and technologies have led to the augmented developments for very large scale integrated circuit designs in electro-magnetic applications. Increasing demands for low power, compact area and superior figure of merit–oriented circuit designs are the trends of the recent research studies. Hence, to accomplish such applications intended for optical communications, the transimpedance amplifier (TIA) was designed.Design/methodology/approachIn this research work, the authors present a multi-layer active feedback structure which mainly composes a transimpedance stage and a gain stage followed by a low pass filter. This structure enables to achieve improved input impedance and superior gain. A simplified cascaded amplifier has also been designed in a hierarchical topology to improvise the noise effect further. The proposed TIA has been designed using Taiwan Semiconductor Manufacturing Company 45 nm complementary metal oxide semiconductor technology. Moreover, the thermal noise has been analyzed at −3 dB bandwidth to prove the reduction in thermal noise with increase in frequency for most of the devices used in the designed circuit.FindingsThe proposed differential TIA circuit was found to obtain the transimpedance gain of 50.1 dBO without applying any external bias current which is almost 8% improvised as compared to the conventional circuit. In addition to this, bandwidth achieved was 2.15 GHz along with only 38 W of power consumption, which is reasonably 100 times improvised in comparison of conventional circuit. Hence, the proposed differential TIA is suitable for the low power optical communications applications intended to work on low supply voltage.Originality/valueThe designed work is done by authors in university lab premises and is not copied from anywhere. To the best of the authors’ knowledge, it is 100% original.

A combinational full adder based on memristors

A combinational full adder based on memristors is considered. Physical and mathematical models of memristors based on hybrid memristor – CMOS logic are proposed for studying the adder. It is shown that these models can be used for modeling in very large-scale integrated circuits design tools, such as the OrCAD. Unlike physical models, mathematical models of elements do not reflect physical properties, but the parameters of their work correspond to physical models. The work contains textual descriptions of the models. As a result of modeling (computational experiment), flow diagrams of the operation of the adder built on these elements are shown, parameters are given (signal propagation time, power dissipation, number of elements, energy efficiency). The developed models can be used to speed up the process of modeling digital integrated circuits using memristors.

Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

Very large-scale integrated circuit design, based on today’s CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leakage power and bring the advantage of nonvolatility. However, radiation-induced soft error is still an issue in such new designs as they need peripheral CMOS components. As a result, these magnetic-based circuits are still susceptive to radiation effects. This paper proposes a radiation hardened and low power magnetic full-adder (MFA) for advanced microprocessors. Comparing with the previous work, the proposed MFA is capable of tolerating any particle strike regardless of the induced charge. Besides, our MFA circuit offers a lower energy consumption in write operation as compared with previous counterparts. We also suggest an incremental modification to the proposed MFA circuit to give it the advantage of full nonvolatility for future nonvolatile microprocessors.

Multimodal Analog Front End for Wearable Bio-Sensors

Wearable sensors afford convenience in daily health monitoring, though many challenges in the development of such systems need to be overcome. Here, we present a low-power, multimodal analog front end (AFE) for wearable health monitoring sensors based on novel system architecture and very large scale integration circuit design methods. The AFE integrated circuit was designed with the standard 65-nm CMOS technology. Three sensor AFEs, bio-potential, photoplethysmography (PPG), and bioelectrical impedance analyser (BIA) were integrated on the same die with an area of 2.5 $\times $ 2.5 mm2. The power consumption for each AFE mode was $ mW and did not exceed 2 mW for all three modes with a 1.2 V power supply. Results from each individual AFE showed high-quality, motion-robust signals (electrocardiogram, PPG, and BIA) that correlated with those obtained from clinical grade gold-standard devices for similar applications. Such multi-functional, non-intrusive systems permit users to effortlessly self-monitor multiple clinically relevant physiological parameters.

KL_GA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design

As the very large-scale integrated circuit designs enter the deep sub-micron era, many-core processors are regarded as promising architectures to keep up with the Moore's law. To provide effective communications between the on-chip components, network-on-chip was proposed as a new paradigm that exhibits better scalability than the traditional buses. There have been previous researches on application mappings to reduce the power consumption, the network latency and the network area overhead. However, some of the previous proposed algorithms such as the Kernighan---Lin algorithm (KL) and some genetic algorithms (GA) have the problem of finding the local best result instead of a global optimal solution. In this paper, we propose a novel application mapping algorithm for the mesh-of-tree network topology, called KL_GA algorithm. Our proposed algorithm takes the advantage of both the Kernighan---Lin algorithm and genetic algorithms to reduce the overall communication cost. Our KL_GA algorithm first generates a mapping solution using a KL-based method. In order to avoid the appearance of premature phenomena, we next apply a GA-based algorithm to get rid of the population trapped in the local optimum and re-generate a new population. Our evaluations show that, compared to the random mapping algorithm, our KL_GA algorithm saves the power by 21.6 % and reduces the network latency by 16.3 % on the average.

An Improved Ant Colony Optimization Algorithm with Crossover Operator

Ant colony algorithm has been widely applied to lots of fields, such as combinatorial optimization, function optimization, system identification, network routing, robot path planning, data mining and large-scale integrated circuit design of integrated wiring, etc. And it achieved good results. But it still has one weak point which is the slowing convergence speed. To aim at the lacks, an improved ACO is presented. This paper studies a kind of improved ant colony algorithm with crossover operator which makes crossover operator among better results at the end of each iteration. The experiment results indicate that the improved ACO is effectual.

High-efficiency pipeline design of binary arithmetic encoder

This paper focuses on the pipeline design of context-based adaptive binary arithmetic coding (CABAC). CABAC is a well-known bottleneck in very large scale integration circuit design of H.264/AVC encoder. Despite its high performance, the tight feedback loops of CABAC make parallelization difficult. Most researchers are concerned about multi-bin processing regardless of pipeline design. However, without pipeline, the overall performance becomes significantly limited. In this paper, the critical path for the hardware implementation of binary arithmetic encoder (BAE) was analyzed in detail. We break down the computing steps to the best extent, and rearrange such steps to the appropriate pipeline to achieve a balanced latency at each stage. Moreover, a new BAE architecture with a five-stage pipeline and one bin per cycle is proposed, the latency of critical path is substantially reduced, and the frequency and throughput rate are improved. An field-programmable gate array implementation of the proposed pipelined architecture in our H.264 encoder is capable of a 190 Mbps encoding rate. A maximum 483 MHz could be achieved on SMIC 0.13 μm technology, which meets the requirements of quad full high-definition encoding at 30fps. The proposed architecture can be utilized in other designs to achieve improved performance.

A Natural Silk Fibroin Protein‐Based Transparent Bio‐Memristor

AbstractThe recent discovery of nanoelectronics memristor devices has opened up a new wave of enthusiasm and optimism in revolutionizing electronic circuit design, marking the beginning of new era for the advancement of neuromorphic, high‐density logic and memory applications. Here a highly non‐linear dynamic response of a bio‐memristor is demonstrated using natural silk cocoon fibroin protein of silkworm, Bombyx mori. A film that is transparent across most of the visible spectrum is obtained with the electronic‐grade silk fibroin aqueous solution of ca. 2% (wt/v). Bipolar memristive switching is demonstrated; the switching mechanism is confirmed to be the filamentary switching as observed by probing local conduction behavior at nanoscale using scanning tunneling microscopy. The memristive transition is elucidated by a physical model based on the carrier trapping or detrapping in silk fibroin films and this appears to be due to oxidation and reduction procedures, as evidenced from cyclic voltammetry measurements. Hence, silk fibroin protein could be used as a biomaterial for bio‐memristor devices for applications in advanced bio‐inspired very large scale integration circuit design as well as in biologically inspired synapse links for energy‐efficient neuromorphic computing.

Failure mechanism analysis of electromigration dominated damage in TiSi2 nanowires

Electromigration-induced damage has been an important concern in very large scale integrated circuit design for a long time and will be a major road block in the pursuit of nanoelectronics devices and next generation power electronics. In this letter, the failure mechanism analysis on two-terminal TiSi2 nanowire devices was reported. Electromigration dominant mass migration is observed and verified by energy dispersive spectroscopy. The contribution of thermomigration is discussed based on temperature simulation. This work provides useful reference for future devices and the failure analysis on nanostructures.

A Proposal for Concurrent Estimation of Static and Dynamic Nonlinearity of ADC

Despite great advances in very large scale integrated-circuit design and manufacturing, performance of even the best available high-speed, high-resolution analog-to-digital converter (ADC) is known to deteriorate while acquiring fast-rising, high-frequency, and nonrepetitive waveforms. Wave-form digitizers (ADCs) used in high-voltage impulse recordings and measurements are invariably subjected to such waveforms. Errors resulting from a lowered ADC performance can be unacceptably high, especially when higher accuracies have to be achieved (e.g., when part of a reference measuring system). Static and dynamic nonlinearities (estimated independently) are vital indices for evaluating performance and suitability of ADCs to be used in such environments. Typically, the estimation of static nonlinearity involves 10-12 h of time or more (for a 12-b ADC) and the acquisition of millions of samples at high input frequencies for dynamic characterization. ADCs with even higher resolution and faster sampling speeds will soon become available. So, there is a need to reduce testing time for evaluating these parameters. This paper proposes a novel and time-efficient method for the simultaneous estimation of static and dynamic nonlinearity from a single test. This is achieved by conceiving a test signal, comprised of a high-frequency sinusoid (which addresses dynamic assessment) modulated by a low-frequency ramp (relevant to the static part). Details of implementation and results on two digitizers are presented and compared with nonlinearities determined by the existing standardized approaches. Good agreement in results and time savings achievable indicates its suitability.

On the possibility of degradation-free field effect transistors

Time-dependent change in threshold voltage, due to generation of interface/bulk traps, degrades drain current of field effect transistors. In this paper, we show—both theoretically and experimentally—the intriguing possibility of designing degradation-free transistors (with time-invariant drain current), where the degradation in threshold voltage is exactly compensated by improvement in mobility. Such transistors would reduce parametric reliability being a key concern for supply voltage scaling and thereby improve integrated circuit performance by minimizing the guard band voltage used in very large scale integrated circuit design.

Test Generation with Unspecified Variable Assignments

ATPG for very large scale integrated circuit designs is an important problem in industry. With the advent of SOC designs, testing and verification of the core-based designs become a challenging problem. This paper presents an algebraic test generation algorithm with unspecified variable assignments. Given a stuck at fault of the circuit with unspecified signals, the proposed algorithm uses a new encoding scheme for unspecified variable assignments, and solves the Boolean satisfiability formula representing the Boolean difference to obtain a test pattern. Experimental results demonstrate the efficiency and feasibility of the proposed algorithm.

Digital integrated circuits: analysis and design

Exponential improvement in functionality and performance of digital integrated circuits has revolutionized the way we live and work. The continued scaling down of MOS transistors has broadened the scope of use for circuit technology to the point that texts on the topic are generally lacking after a few years. The second edition of Digital Integrated Circuits: Analysis and Design focuses on timeless principles with a modern interdisciplinary view that will serve integrated circuits engineers from all disciplines for years to come. Providing a revised instructional reference for engineers involved with Very Large Scale Integrated Circuit design and fabrication, this book delves into the dramatic advances in the field, including new applications and changes in the physics of operation made possible by relentless miniaturization. This book was conceived in the versatile spirit of the field to bridge a void that had existed between books on transistor electronics and those covering VLSI design and fabrication as a separate topic. Like the first edition, this volume is a crucial link for integrated circuit engineers and those studying the field, supplying the cross-disciplinary connections they require for guidance in more advanced work. For pedagogical reasons, the author uses SPICE level 1 computer simulation models but introduces BSIM models that are indispensable for VLSI design. This enables users to develop a strong and intuitive sense of device and circuit design by drawing direct connections between the hand analysis and the SPICE models. With four new chapters, more than 200 new illustrations, numerous worked examples, case studies, and support provided on a dynamic website, this text significantly expands concepts presented in the first edition.

Global optimization for digital MOS circuits performance

Apart from maximization of parametric yield, minimization of the spread in performance functions due to process variation is of extreme importance in very large scale integrated circuit design. To achieve efficient minimization of the spread, a novel algorithm based on the genetic algorithm and global approximation methods is proposed. The algorithm operates in two stages designated as coarse and fine optimization stages and adjusts design parameter set to simultaneously achieve the target performance and reduction in performance spread. The algorithm has distinctive features, such as global optimum design, subexponential complexity algorithm for N-P complete problem of global optimization, and simultaneous optimization of many functions. The algorithm is demonstrated using four design examples.

Implementing Parallel Counters with Four-Valued Threshold Logic

Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing state-of-the-art digital signal processing systems in large-scale-integrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50-percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.

The state of large-scale integrated circuit design automation

The state of large-scale integrated circuit design automation