High-efficiency pipeline design of binary arithmetic encoder

Abstract

This paper focuses on the pipeline design of context-based adaptive binary arithmetic coding (CABAC). CABAC is a well-known bottleneck in very large scale integration circuit design of H.264/AVC encoder. Despite its high performance, the tight feedback loops of CABAC make parallelization difficult. Most researchers are concerned about multi-bin processing regardless of pipeline design. However, without pipeline, the overall performance becomes significantly limited. In this paper, the critical path for the hardware implementation of binary arithmetic encoder (BAE) was analyzed in detail. We break down the computing steps to the best extent, and rearrange such steps to the appropriate pipeline to achieve a balanced latency at each stage. Moreover, a new BAE architecture with a five-stage pipeline and one bin per cycle is proposed, the latency of critical path is substantially reduced, and the frequency and throughput rate are improved. An field-programmable gate array implementation of the proposed pipelined architecture in our H.264 encoder is capable of a 190 Mbps encoding rate. A maximum 483 MHz could be achieved on SMIC 0.13 μm technology, which meets the requirements of quad full high-definition encoding at 30fps. The proposed architecture can be utilized in other designs to achieve improved performance.