Implementing Parallel Counters with Four-Valued Threshold Logic

Abstract

Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing state-of-the-art digital signal processing systems in large-scale-integrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50-percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.