Abstract
Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have