Large-scale Hardware Research Articles

Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks

Spiking Neural Networks (SNNs) exhibit the strong capability to address spatiotemporal dynamic problems. Recent research has explored the hardware SNN systems to solve the spatiotemporal problems in real-time. The Network-on-Chip (NoC) is an effective scheme for building large-scale hardware SNNs. However, for the existing NoC-based hardware SNNs, large area overhead and hardware power are consumed by their interconnections, because of complex topologies and router structures. Therefore, in this work a novel Unidirectional and Hierarchical on-Chip Interconnected Architecture (UHCIA) is proposed to address this problem. The proposed UHCIA mainly combines the novel hybrid topology of unidirectional multiple loops and rings, and uses a deflection router technique. Experimental results show that compared to other works, the UHCIA achieves ∼23.6X of area reduction and ∼6.4X of power reduction, with high system throughput and biological real-time computations.

Low-error, high-speed, and large-scale hardware implementation of retinal photoreceptor cells: Cone and rod cells

In recent times, there has been a significant focus on creating prosthetics and medical interventions to aid in the treatment of diseases, recovery, and the improvement of biological functions. Researchers have particularly directed their attention toward developing hardware models for delicate biological parts such as the brain, heart, nervous system, and. One area of particular interest is the retina, which is the thinnest and innermost layer of the eye. This research paper focuses on the development of a high-speed and low-error hardware implementation for retinal cone and rod cells. Current mathematical models often use multiple nonlinear functions to describe the behavior of these cells. However, these nonlinear functions can sometimes be limiting in terms of speed. In this study, we explore the use of trigonometric functions to approximate the non-linear properties of retinal cone and rod cells, allowing for improved performance. The results of the simulation show that the suggested model is in line with the functioning of primary cone and rod cells, particularly in relation to time characteristics, dynamic response, and margin of error. By implementing the proposed model in Large-Scale (300 cell) on a Virtex-5 Field Programmable Gate Array (FPGA) board, notable benefits were observed. One of these advantages includes increasing the synthesis frequency of the proposed model by 3.35 and 3.44 times faster than the original model for the cone cell and rod cell, respectively. Another advantage is the ability to implement 300 cells of the proposed models on the FPGA, compared to the implementation of a single cell of the original models, with only a two-fold increase in the amount of hardware resources used. The proposed framework is legitimate and features a compact hardware size and suitable network frequency, as demonstrated by the outcomes from implementing the hardware on the Virtex-5 reconfigurable board (FPGA).

Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code

Verification of hardware design code is crucial for the quality assurance of hardware products. Being an indispensable part of verification, localizing bugs in the hardware design code is significant for hardware development but is often regarded as a notoriously difficult and time-consuming task. Thus, automated bug localization techniques that could assist manual debugging have attracted much attention in the hardware community. However, existing approaches are hampered by the challenge of achieving both demanding bug localization accuracy and facile automation in a single method. Simulation-based methods are fully automated but have limited localization accuracy, slice-based techniques can only give an approximate range of the presence of bugs, and spectrum-based techniques can also only yield a reference value for the likelihood that a statement is buggy. Furthermore, formula-based bug localization techniques suffer from the complexity of combinatorial explosion for automated application in industrial large-scale hardware designs. In this work, we propose Kummel, a K nowledge-a u g m ented m utation-bas e d bug loca l ization for hardware design code to address these limitations. Kummel achieves the unity of precise bug localization and full automation by utilizing the knowledge augmentation through mutation analysis. To evaluate the effectiveness of Kummel, we conduct large-scale experiments on 76 versions of 17 hardware projects by seven state-of-the-art bug localization techniques. The experimental results clearly show that Kummel is statistically more effective than baselines, e.g., our approach can improve the seven original methods by 64.48% on average under the RImp metric. It brings fresh insights of hardware bug localization to the community.

Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems

Industry is moving towards large-scale hardware systems that bundle processor cores, memories, accelerators, and so on. via 2.5D integration. These components are fabricated separately as chiplets and then integrated using an interposer as an interconnect carrier. This new design style is beneficial in terms of yield and economies of scale, as chiplets may come from various vendors and are relatively easy to integrate into one larger sophisticated system. However, the benefits of this approach come at the cost of new security challenges, especially when integrating chiplets that come from untrusted or not fully trusted, third- party vendors. In this work, we explore these challenges for modern interposer-based systems of cache-coherent, multi-core chiplets. First, we present basic coherence-oriented hardware Trojan attacks that pose a significant threat to chiplet-based designs and demonstrate how these basic attacks can be orchestrated to pose a significant threat to interposer-based systems. Second, we propose a novel scheme using an active interposer as a generic, secure-by-construction platform that forms a physical root of trust for modern 2.5D systems. The implementation of our scheme is confined to the interposer, resulting in little cost and leaving the chiplets and coherence system untouched. We show that our scheme prevents a range of coherence attacks with low overheads on system performance, ∼4%. Further, we demonstrate that our scheme scales efficiently as system size and memory capacities increase, resulting in reduced performance overheads.

Printable Epsilon‐Type Structure Transistor Arrays with Highly Reliable Physical Unclonable Functions (Adv. Mater. 16/2023)

Physical Unclonable Functions In article number 2210621, Bowen Zhu, Hong Wang, and co-workers use printed epsilon-type-structure transistor arrays with a modified indium tin oxide coffee-ring structure to construct physical unclonable functions (PUFs) that demonstrate near-ideal uniformity, uniqueness, randomness, reliability, and low power consumption. Additionally, the PUFs are secure against attack by a powerful machine-learning model without post-processing. The epsilon-type structure provides a printable, simple strategy for high-quality and large-scale hardware secure primitives.

Emergency Power Supply System for Critical Infrastructures: Design and Large Scale Hardware Demonstration

Emergency Power Supply System for Critical Infrastructures: Design and Large Scale Hardware Demonstration

BTBT Based LIF Junctionless FET Neuron With Plausible Mimicking Efficiency

Amid the quest for nanoscale devices to mimic the biological neuronal dynamics, this article demonstrates a SOI Junctionless Field Effect Transistor (JLFET) based leaky integrate and fire (LIF) neuron in sub-20 nm technology. The band-to-band-tunneling (BTBT) mechanism is considered to imitate the leaky-integration behavior. As JLFET has strongly doped channel that supports fully depletion in the OFF state with considerable band overlapping of channel and drain regions that is subsequently allowing the BTBT in lateral direction. Moreover, the proposed device based LIF neuron requires neither metallurgical junction nor back gate bias to induce the floating body to confine the excess carrier. And, it requires only 0.4 V of supply voltage, which is much lower compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons and it shows a GHz range of spiking frequency i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 8 orders greater than biological neuron. Hence, it presumes that the proposed SOI JLFET based LIF neuron is more suitable for large scale hardware implementation of spiking neural network (SNN) due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

A Confidentiality-based data Classification-as-a-Service (C2aaS) for cloud security

Rapid development and massive use of Information Technology (IT) have since produced a massive amount of electronic data. In tandem, the demand for data outsourcing and the associated data security is increasing exponentially. Small organizations are often finding it expensive to save and process their huge amount of data, and keep the data secure from unauthorized access. Cloud computing is a suitable and affordable platform to provide services on user demand. The cloud platform is preferable used by individuals, Small, and Medium Enterprises (SMEs) that cannot afford large-scale hardware, software, and security maintenance cost. Storage and processing of big data in the cloud are becoming the key appealing features to SMEs and individuals. However, the processing of big data in the cloud is facing two issues such as security of stored data and system overload due to the volume of the data. These storage methods are plain text storage and encrypted text storage. Both methods have their strengths and limitations. The fundamental issue in plain text storage is the high risk of data security breaches; whereas, in encrypted text storage, the encryption of complete file data may cause system overload. This paper propose a feasible solution to address these issues with a new service model called Confidentiality-based Classification-as-a-Service (C2aaS) that performs data processing by treating data dynamically according to the data security level in preparation for data storing in the cloud. In comparison to the conventional methods, our proposed service model is strongly showing good security for confidential data and is proficient in reducing cloud system overloading.

Electronegative metal dopants improve switching variability in Al2O3 resistive switching devices

Resistive switching random access memories (RRAMs) promise to overcome the limitation of time- and energy-consumption set by increased training demand in the deep neural network. These devices enable the colocation of memory and processing by storing and utilizing information in the form of conductive networks, such as those made of oxygen vacancies. However, the inherent stochastic nature of atomic motion results in poor reliability and high switching variability in these devices, hindering their widespread use. In this paper, the authors propose a method to substantially reduce the switching variability of RRAM devices by doping the RRAM oxide electrolyte with electronegative metals. They find that electronegative metals reduce the oxygen vacancy formation energy, thereby pinning the conductive filament formation along fixed, predictable paths. This improved reliability enables multibit switching and can facilitate integration into large-scale hardware neural networks.

Linear Frequency Modulation of NbO2-Based Nanoscale Oscillator With Li-Based Electrochemical Random Access Memory for Compact Coupled Oscillatory Neural Network.

Oscillatory neural network (ONN)-based classification of clustered data relies on frequency synchronization to injected signals representing input data, showing a more efficient structure than a conventional deep neural network. A frequency tunable oscillator is a core component of the network, requiring energy-efficient, and area-scalable characteristics for large-scale hardware implementation. From a hardware viewpoint, insulator-metal transition (IMT) device-based oscillators are attractive owing to their simple structure and low power consumption. Furthermore, by introducing non-volatile analog memory, non-volatile frequency programmability can be obtained. However, the required device characteristics of the oscillator for high performance of coupled oscillator have not been identified. In this article, we investigated the effect of device parameters of IMT oscillator with non-volatile analog memory on coupled oscillators network for classification of clustered data. We confirmed that linear conductance response with identical pulses is crucial to accurate training. In addition, considering dispersed clustered inputs, a wide synchronization window achieved by controlling the hold voltage of the IMT shows resilient classification. As an oscillator that satisfies the requirements, we evaluated the NbO2-based IMT oscillator with non-volatile Li-based electrochemical random access memory (Li-ECRAM). Finally, we demonstrated a coupled oscillator network for classifying spoken vowels, achieving an accuracy of 85%, higher than that of a ring oscillator-based system. Our results show that an NbO2-based oscillator with Li-ECRAM has the potential for an area-scalable and energy-efficient network with high performance.

Ultrahigh-Speed In-Memory Electronics Enabled by Proximity-Oxidation-Evolved Metal Oxide Redox Transistors.

The pursuit of a universal device that combines nonvolatile multilevel storage, ultrafast writing/erasing speed, nondestructive readout, and embedded processing with low power consumption demands the development of innovative architectures. Although thin-film transistors and redox-based resistive-switching devices have independently been proven to be ideal building blocks for data processing and storage, it is still difficult to achieve both well-controlled multilevel memory and high-precision ultrafast processing in a single unit, even though this is essential for the large-scale hardware implementation of in-memory computing. In this work, an ultrafast (≈42ns) and programable redox thin-film transistor (ReTFT) memory made of a proximity-oxidation-grown TiO2 layer is developed, which has on/off ratio of 105 , nonvolatile multilevel analog storage with a long retention time, strong durability, and high reliability. Utilizing the proof-of-concept ReTFTs, circuits capable of performing fundamental NOT, AND, and OR operations with reconfigurable logic-in-memory processing are developed. Further, on-demand signal memory-processing operations, like multi-terminal addressable memory, learning, pattern recognition, and classification, are explored for prospective application in neuromorphic hardware. This device, which operates on a fundamentally different mechanism, presents an alternate solution to the problems associated with the creation of high-performing in-memory processing technology.

Neuromorphic Behaviors of the 4-Lobe Chua Corsage Memristor

Neuromorphic computing plays an important role in brain-inspired computers, which can solve complex problems with higher efficiency and lower energy. As a promising candidate of neuromorphic devices, a locally active memristor has the ability to emulate complex neuromorphic functions, which has the potential to implement large-scale hardware spiking neural networks to unleash the efficiency and intelligence of the brain. In this paper, we analyze the characteristics of the locally active 4-lobe Chua corsage memristor (CCM) using small-signal equivalent circuits. In addition, we design a CCM-based third-order neuron circuit and illustrate its rich neuromorphic behaviors near the edge of chaos, such as self-sustained oscillation, periodic spiking, chaos, transient chaos, resting states, burst-number adaption, spike latency, and refractory period. Furthermore, collective behaviors such as exotic chimera states (e.g. coherent and incoherent patterns) have been observed in the ring neural network made of third-order memristive neurons with linear and nonlocal coupling.

Fault tolerance in big data storage and processing systems: A review on challenges and solutions

Big data systems are sufficiently stable to store and process a massive volume of rapidly changing data. However, big data systems are composed of large-scale hardware resources that make their subspecies easily fail. Fault tolerance is the main property of such systems because it maintains availability, reliability, and constant performance during faults. Achieving an efficient fault tolerance solution in a big data system is challenging because fault tolerance must meet some constraints related to the system performance and resource consumption. This study aims to provide a consistent understanding of fault tolerance in big data systems and highlights common challenges that hinder the improvement in fault tolerance efficiency. The fault tolerance solutions applied by previous studies intended to address the identified challenges are reviewed. The paper also presents a perceptive discussion of the findings derived from previous studies and proposes a list of future directions to address the fault tolerance challenges.

Demonstration of an UltraLow Energy PD-SOI FinFET Based LIF Neuron for SNN

In this article, partially depleted silicon on insulator (PD-SOI) FinFET based LIF neuron is demonstrated to mimic biological neuronal behaviour with aid of well-calibrated 3D TCAD simulation. The floating body effect of PD-SOI FinFET is used to store the holes generated by the impact ionisation (&#x2018;II&#x2019;), which exhibits the integration phenomenon and recombination manifests the leaky function. It shows 5.4 fJ of energy per spike, which is significantly lower than other FinFET based neurons reported till date. Moreover, it needs only 1.8 V of supply voltage, which is lower as compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons. The proposed PD-SOI FinFET LIF neuron shows megahertz range of spiking frequency, that is <inline-formula><tex-math notation="LaTeX">$\sim 10 ^{5}$</tex-math></inline-formula>&#x00D7; higher than biological neuron (<inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>1-10 Hz). Furthermore, the effective area of the FinFET is optimized as 0.023 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$ ^{2}$</tex-math></inline-formula>. Thus, the proposed PD-SOI FinFET based LIF neuron is more attractive for large scale hardware implementation of SNN, due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

A Fast Weight Transfer Method for Real-Time Online Learning in RRAM-Based Neuromorphic System

In this work, a synaptic weight transfer method for a neuromorphic system based on resistive-switching random-access memory (RRAM) is proposed and validated. To implement the on-chip trainable neuromorphic system which utilizes large-scale hardware synapse units, a fast and reliable write scheme needs to be established. Based on the experimental results, it is confirmed that the gradual set and full reset operation is the most suitable operation scheme for fast programming due to the fundamental reliability characteristics of the resistive-switching memory cell. Also, the superiority of this programming method using the proposed RRAM compact model is demonstrated. In addition, a one weight/one synaptic device structure is newly adopted for realizing high-density synapse arrays by using a nonnegative weight constraint in supervised learning. Finally, the pattern recognition accuracies obtained at the software and hardware levels are compared.

Intelligent fault diagnosis of rotating machinery based on a novel lightweight convolutional neural network

For most existing fault diagnosis methods, feature extraction is always based on a complex artificial design and the complete feature extraction from an original signal. With the gradual complication of modern industrial machinery and equipment, it has become more difficult for traditional feature extractors to achieve the desired results. Deep convolutional neural networks (DCNNs) have been developed as effective techniques for fault classification but require large-scale high-intensity computing and prohibitive hardware resource requirements. This paper proposes a lightweight CNN that can be easily used for the fault diagnosis of rotating machinery by adjusting the network structure and optimizing the network. First, the raw vibration acceleration signal is transformed into a two-dimensional gray image. Second, two mature and commonly used modules named LeNet and NIN are combined to form a new model with a simple structure. Then, through parameter adjustment and optimization, an improved and optimized CNN with a lightweight structure and fewer parameters is constructed. The experimental verification has shown that this method has high accuracy and stability in fault diagnosis. Finally, the application of this new network for the fault diagnosis of rolling bearings with different damage levels but similar fault types shows high diagnostic accuracy and good generalization ability. In addition, we attempt to explain how the feature filters of a CNN work by visualizing the convolutional layer of the network.

Hybrid CMOS/memristor crossbar structure for implementing hopfield neural network

Competent hardware implementation of artificial neural networks is still an important contest. In recent literature, memristor has been introduced as a promising candidate for synapses implementation. However, integrating a memristive circuit with neuron hardware is auspicious research with challenging issues. In this paper, a scalable circuit-level hybrid CMOS/memristor hardware is introduced for implementing a Hopfield neural network. The proposed circuit is fully compatible with the crossbar structure. The performance of the proposed hardware is evaluated for different scales and compared with its software-based counterpart. Moreover, the accuracy of large-scale hardware for Hopfield neural network with 45 neurons and 4320 memristors is evaluated. It is demonstrated that the performance of the circuit is in the line of the software simulation. In comparison with similar works, the proposed circuit consumes 2000 times less energy and retrieves patterns 130 times faster. The implemented circuit is a step toward a general and feasible memristive hardware implementation for recurrent neural networks.

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.

High Performance SiGe HBT Performance Variability Learning by Utilizing Neural Networks and Technology Computer Aided Design

Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values.The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM.The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature.

Development of a research platform for BEPC II accelerator fault diagnosis

BackgroundBEPC II is an electron–positron collider with a beam energy of 1.89 GeV and luminosity of 1 × 1033 cm−2 s−1. Being a complex accelerator, fault diagnostics both in an accurate manner and in time are often challenging during its operation.PurposeThe fault diagnosis research platform is capable of locating and resolving faults on time, thus can largely improve the operation of BEPCII by reducing downtime due to machine fault and consequently satisfying the demand for fault diagnosis of a complex system.MethodsMaking full use of the existing large-scale hardware foundation, abundant data resources and previous experiences, a fault diagnosis research platform was built by applying data mining, machine learning and other related algorithms to carry out specific fault analysis on the entire system.ConclusionThe fault diagnosis research platform has been developed with implemented functions of data query, statistics and analysis. Partial fault diagnoses of the three subsystems have been realized. The 4W1 power supply fault has been successfully discovered, and effective solutions have been subsequently provided.