Low-error, high-speed, and large-scale hardware implementation of retinal photoreceptor cells: Cone and rod cells

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In recent times, there has been a significant focus on creating prosthetics and medical interventions to aid in the treatment of diseases, recovery, and the improvement of biological functions. Researchers have particularly directed their attention toward developing hardware models for delicate biological parts such as the brain, heart, nervous system, and. One area of particular interest is the retina, which is the thinnest and innermost layer of the eye. This research paper focuses on the development of a high-speed and low-error hardware implementation for retinal cone and rod cells. Current mathematical models often use multiple nonlinear functions to describe the behavior of these cells. However, these nonlinear functions can sometimes be limiting in terms of speed. In this study, we explore the use of trigonometric functions to approximate the non-linear properties of retinal cone and rod cells, allowing for improved performance. The results of the simulation show that the suggested model is in line with the functioning of primary cone and rod cells, particularly in relation to time characteristics, dynamic response, and margin of error. By implementing the proposed model in Large-Scale (300 cell) on a Virtex-5 Field Programmable Gate Array (FPGA) board, notable benefits were observed. One of these advantages includes increasing the synthesis frequency of the proposed model by 3.35 and 3.44 times faster than the original model for the cone cell and rod cell, respectively. Another advantage is the ability to implement 300 cells of the proposed models on the FPGA, compared to the implementation of a single cell of the original models, with only a two-fold increase in the amount of hardware resources used. The proposed framework is legitimate and features a compact hardware size and suitable network frequency, as demonstrated by the outcomes from implementing the hardware on the Virtex-5 reconfigurable board (FPGA).