Large-scale Field Programmable Gate Arrays Research Articles

Large-Scale Bio-Inspired FPGA Models for Path Planning.

The hippocampus provides significant inspiration for spatial navigation and memory in both humans and animals. Constructing large-scale spiking neural network (SNN) models based on the biological neural systems is an important approach to comprehend the computational principles and cognitive function of the hippocampus. Such models are usually implemented on neuromorphic computing platforms, which often have limited computing resources that constrain the achievable scale of the network. This work introduces a series of digital design methods to realize a Field-Programmable Gate Array (FPGA) friendly SNN model. The methods include FPGA-friendly nonlinear calculation modules and a fixed-point design algorithm. A brain-inspired large-scale SNN of ∼21 k place cells for path planning is mapped on FPGA. The results show that the path planning tasks in different environments are finished in real-time and the firing activities of place cells are successfully reproduced. With these methods, the achievable network size on one FPGA chip is increased by 1595 times with higher resource usage efficiency and faster computation speed compared to the state-of-the-art.

Simplified digital coherent-based beyond-100G optical access systems for B5G/6G [Invited

In this paper, we review the latest progress in the simplified digital coherent technologies suitable for future beyond-100G optical access systems, which will be a key optical transport platform for meeting the very wide range of extreme requirements of beyond-5G (B5G) and 6G users. As the centerpiece of beyond-100G optical access systems, the technical challenges and recent demonstrations of ultimate-capacity passive optical network systems carrying more than 100 Gb/s per wavelength by using simplified digital coherent technologies incorporating low-complexity digital signal processing (DSP) are presented. In addition, to facilitate the implementation of these relatively large-scale digital coherent technologies in the optical access area, which has strict cost, power consumption, and size restraints, the rapid progress in compact optical transceiver form factors and optical devices heading toward 400 Gb/s-based Ethernet transceivers for the 80 km range (400G-ZR) and over 800 Gb/s short-reach applications based on the digital coherent technologies are also discussed. Furthermore, the recent expansion of simplified digital coherent-based optical access systems such as optical space communications and their latest experimental demonstrations are introduced as an alternative evolution of beyond-100G optical access systems, going hand in hand with the reduction of complexity of the real-life digital coherent platforms such as the DSP large-scale integration and the large-scale field programmable gate arrays.

High-performance parallel computing for next-generation holographic imaging

Holography is a method of recording and reproducing three-dimensional (3D) images, and the widespread availability of computers has encouraged the development of holographic 3D screens (electroholography). However, the technology has not yet been used in practical applications because a hologram requires an enormous volume of data and modern computing power is inadequate to process this volume of data in real time. Here, we show that a special-purpose holography computing board, which uses eight large-scale field-programmable gate arrays, can be used to generate 108-pixel holograms that can be updated at a video frame rate. With our approach, we achieve a parallel operation of 4,480 hologram calculation circuits on a single board, and by clustering eight of these boards, we can increase the number of parallel calculations to 35,840. Using a 3D image composed of 7,877 points, we show that 108-pixel holograms can be updated at a video rate, thus allowing 3D movies to be projected. We also demonstrate that the system speed scales up in a linear manner as the number of parallel circuits is increased. The system operates at 0.25 GHz with an effective speed equivalent to 0.5 petaflops (1015 floating-point operations per second), matching that of a high-performance computer. A special-purpose holography computing board, which uses eight large-scale field-programmable gate arrays, can be used to generate 108-pixel holograms that can be updated at a video frame rate.

Superconducting Magnetic Field Programmable Gate Array

Field-programmable gate arrays (FPGAs) provide a significantly cheaper solution for various applications in traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA will be very useful. Towards developing such an SFQ-specific FPGA, new designs of FPGA subcircuits for both synchronous and asynchronous operation of SFQ circuits are presented in this paper. Magnetic Josephson junctions (MJJs) are used as bias limiting junctions in energy-efficient rapid SFQ (ERSFQ) biasing to implement programmable switches in various subcircuits of the proposed FPGA fabric. Designs of all FPGA subcircuits are developed and are verified through circuit simulation. Verilog hardware description language (HDL) models are also developed for all FPGA circuit blocks to facilitate large-scale FPGA simulations for the implementation of the desired circuit on the proposed FPGA fabric. Designs of a few subcircuits with switches based on nondestructive readout cell are also given in the current paper for better comparison with MJJ switch based counterparts. Programming of MJJ-based switches is based on the ability to control the critical current of MJJs externally. Recent implementations of SFQ decoder is proposed for accessing individual MJJs through the current lines in a crossbar structure. Estimations for the area and power consumption are much better in comparison to previous attempts at designing an SFQ specific FPGA.

Special-purpose computer HORN-5 for a real-time electroholography

In electroholography, a real-time reconstruction is one of the grand challenges. To realize it, we developed a parallelized high performance computing board for computer-generated hologram, named HORN-5 board, where four large-scale field programmable gate array chips were mounted. The number of circuits for hologram calculation implemented to the board was 1,408. The board calculated a hologram at higher speed by 360 times than a personal computer with Pentium4 processor. A personal computer connected with four HORN-5 boards calculated a hologram of 1,408 x 1,050 made from a three-dimensional object consisting of 10,000 points at 0.0023 s. In other words, beyond at video rate (30 frames / s), it realized a real-time reconstruction.

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.

Matching-based algorithm for FPGA channel segmentation design

Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multi-level matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work.