Large-scale Circuits Research Articles

Chemical Reaction Simulator on Quantum Computers by First Quantization (II)─Basic Treatment: Implementation.

Chemical simulation is a key application area that can leverage the power of quantum computers. A chemical simulator that implements a grid-based first quantization method has promising characteristics, but an implementation fully in quantum circuits seems to have not been published. Here, we present "crsQ" (chemical reaction simulator Q), which is a quantum circuit generator that generates such a chemical simulator. The generated simulator is capable of antisymmetrization of the initial wave function and time-evolution of the wave function based on the Suzuki-Trotter decomposition. The potential energy term of the Hamiltonian is implemented using arithmetic gates, such as adders, subtractors, multipliers, dividers, and square roots. Circuit diagrams and output samples are shown. The number of qubits in the circuits scales on the order of O(η log η), where η is the number of electrons. Each component of the generated circuit was verified in unit tests. Along with this development, we designed frameworks to ease the development of large-scale circuits, namely, a temporary qubit allocation framework and an abstract syntax tree framework for arithmetic formulas. These frameworks are expected to be useful in large-scale quantum circuit generators.

A fixed phase tunable directional coupler based on coupling tuning

The field of photonic integrated circuits has witnessed significant progress in recent years, with a growing demand for devices that offer high-performance reconfigurability. Due to the inability of conventional tunable directional couplers (TDCs) to maintain a fixed phase while tuning the reflectivity, Mach-Zehnder interferometers (MZIs) are employed as the primary building blocks for reflectivity tuning in constructing large-scale circuits. However, MZIs are prone to fabrication errors due to the need for perfect balanced directional couplers to achieve 0-1 reflectivity, which hinders their scalability. In this study, we introduce a design of a TDC based on coupling constant tuning in the thin film Lithium Niobate platform and present an optimized design. Our optimized TDC design enables arbitrary reflectivity tuning while ensuring a consistent phase across a wide range of operating wavelengths. Furthermore, it exhibits fewer bending sections than MZIs and is inherently resilient to fabrication errors in waveguide geometry and coupling length compared to both MZIs and conventional TDCs. Our work contributes to developing high-performance photonic integrated circuits with implications for various fields, including optical communication systems and quantum information processing.

Multi-objective simulated annealing-based quantum circuit cutting for distributed quantum computation

In the current noisy intermediate-scale quantum (NISQ) era, the number of qubits and the depth of quantum circuits in a quantum computer are limited because of complex operation among increasing number of qubits, low-fidelity quantum gates under noise, and short coherence time of physical qubits. However, with distributed quantum computation (DQC) in which multiple small-scale quantum computers cooperate, large-scale quantum circuits can be implemented. In DQC, it is a key step to decompose large-scale quantum circuits into several small-scale subcircuits equivalently. In this paper, we propose a quantum circuit cutting scheme for the circuits consisting of only single-qubit gates and two-qubit gates. In the scheme, the number of non-local gates and the rounds of subcircuits operation are minimized by using the multi-objective simulated annealing (MOSA) algorithm to cluster the gates and to choose the cutting positions whilst using non-local gates. A reconstruction process is also proposed to calculate the probability distribution of output states of the original circuit. As an example, the 7-qubit circuit of Shor algorithm factoring 15 is used to verify the algorithm. Five cutting schemes are recommended, which can be selected according to practical requirements. Compared with the results of the mixing integer programming (MIP) algorithm, the number of execution rounds is efficiently reduced by slightly increasing the number of nonlocal gates.

A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits

Topological quantum error correction (TQEC) using the surface code is among the most promising techniques for fault-tolerant quantum circuits. The required resource of a TQEC circuit can be modeled as a space-time volume of a three-dimensional diagram by describing the defect movement along the time axis. For large-scale complex problems, it is crucial to minimize the space-time volume for a quantum algorithm with a reasonable physical qubit number and computation time. Previous work proposed an automated tool for bridge compression on a large-scale TQEC circuit. However, the existing automated bridge compression is only for dual defects and not for primal defects. This paper presents an algorithm to simultaneously perform bridge compression on primal and dual defects. In addition, the automatic compression algorithm performs initialization/measurement simplification and flipping to improve the compression. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 53%.

Large-Scale Mechanistic Models of Brain Circuits with Biophysically and Morphologically Detailed Neurons.

Understanding the brain requires studying its multiscale interactions from molecules to networks. The increasing availability of large-scale datasets detailing brain circuit composition, connectivity, and activity is transforming neuroscience. However, integrating and interpreting this data remains challenging. Concurrently, advances in supercomputing and sophisticated modeling tools now enable the development of highly detailed, large-scale biophysical circuit models. These mechanistic multiscale models offer a method to systematically integrate experimental data, facilitating investigations into brain structure, function, and disease. This review, based on a Society for Neuroscience 2024 MiniSymposium, aims to disseminate recent advances in large-scale mechanistic modeling to the broader community. It highlights (1) examples of current models for various brain regions developed through experimental data integration; (2) their predictive capabilities regarding cellular and circuit mechanisms underlying experimental recordings (e.g., membrane voltage, spikes, local-field potential, electroencephalography/magnetoencephalography) and brain function; and (3) their use in simulating biomarkers for brain diseases like epilepsy, depression, schizophrenia, and Parkinson's, aiding in understanding their biophysical underpinnings and developing novel treatments. The review showcases state-of-the-art models covering hippocampus, somatosensory, visual, motor, auditory cortical, and thalamic circuits across species. These models predict neural activity at multiple scales and provide insights into the biophysical mechanisms underlying sensation, motor behavior, brain signals, neural coding, disease, pharmacological interventions, and neural stimulation. Collaboration with experimental neuroscientists and clinicians is essential for the development and validation of these models, particularly as datasets grow. Hence, this review aims to foster interest in detailed brain circuit models, leading to cross-disciplinary collaborations that accelerate brain research.

Structural designs and synthesis of co-polycarbonates with cyclohexyl and fluorene structures: Low-dielectric constant, high solubility, and superior mechanical properties

The rapid developments of high-speed communication and large-scale integrated circuits have accelerated the research for insulating dielectric materials with low dielectric constant, low dielectric loss, and good mechanical properties. In this study, a series of polycarbonate resins containing cyclohexyl and fluorene structures are synthesized by melt transesterification, which is low dielectric, highly thermally resistant, and soluble. The effects of fluorene structure contents on the properties of a co-polycarbonate resin were studied systematically. The results showed that the non-polar fluorene group could reduce the molecular polarization of co-polycarbonate, resulting in low permittivity of co-polycarbonate are 2.41-2.71@1MHz. In addition, the resin has excellent solubility and can be dissolved in NMP, CH2Cl2, THF, and other solvents at room temperature. Furthermore, the co-polycarbonate resins also exhibit superior heat resistance with glass transition temperature (Tg) of 160.6-173.1 °C as well as admirable mechanical properties with a tensile strength of 50.54-70.72 MPa. This makes it a promising candidate for high-speed communications and large-scale integrated circuits.

Robust Qubit Mapping Algorithm via Double-Source Optimal Routing on Large Quantum Circuits

Qubit mapping is a critical aspect of implementing quantum circuits on real hardware devices. Currently, the existing algorithms for qubit mapping encounter difficulties when dealing with larger circuit sizes involving hundreds of qubits. In this article, we introduce an innovative qubit mapping algorithm, Duostra, tailored to address the challenge of implementing large-scale quantum circuits on real hardware devices with limited connectivity. Duostra operates by efficiently determining optimal paths for double-qubit gates and inserting SWAP gates accordingly to implement the double-qubit operations on real devices. Together with two heuristic scheduling algorithms, Limitedly Exhaustive Search and Shortest-Path Estimation, it yields results of good quality within a reasonable runtime, thereby striving toward achieving quantum advantage. Experimental results showcase our algorithm’s superiority, especially for large circuits beyond the NISQ era. For example, on large circuits with more than 50 qubits, we can reduce the mapping cost on an average 21.75% over the virtual best results among QMAP, t \(|ket\rangle\) , Qiskit, and SABRE. Besides, for mid-size circuits such as the SABRE-large benchmark, we improve the mapping costs by 4.5%, 5.2%, 16.3%, 20.7%, and 25.7%, when compared to QMAP, TOQM, t \(|ket\rangle\) , Qiskit, and SABRE, respectively.

Electronics and Optoelectronics Based on Tellurium.

As a true 1Dsystem, group-VIA tellurium (Te) is composed of van der Waals bonded molecular chains within a triangular crystal lattice. This unique crystal structure endows Te with many intriguing properties, including electronic, optoelectronic, thermoelectric, piezoelectric, chirality, and topological properties. In addition, the bandgap of Te exhibits thickness dependence, ranging from 0.31eV in bulk to 1.04eV in the monolayer limit. These diverse properties make Te suitable for a wide range of applications, addressing both established and emerging challenges. This review begins with an elaboration of the crystal structures and fundamental properties of Te, followed by a detailed discussion of its various synthesis methods, which primarily include solution phase, and chemical and physical vapor deposition technologies. These methods form the foundation for designing Te-centered devices. Then the device applications enabled by Te nanostructures are introduced, with an emphasis on electronics, optoelectronics, sensors, and large-scale circuits. Additionally, performance optimization strategies are discussed for Te-based field-effect transistors. Finally, insights into future research directions and the challenges that lie ahead in this field are shared.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Inverse-designed taper configuration for the enhancement of integrated 1 × 4 silicon photonic power splitters

Abstract Once light is coupled to a photonic chip, its efficient distribution in terms of power splitting throughout silicon photonic circuits is very crucial. We present two types of 1 × 4 power splitters with different splitting ratios of 1:1:1:1 and 2:1:1:2. Various taper configurations were compared and analyzed to find the suitable configuration for the power splitter, and among them, parabolic tapers were chosen. The design parameters of the power splitter were determined by means of solving inverse design problems via incorporating particle swarm optimization that allows for overcoming the limitation of the intuition-based brute-force approach. The front and rear portions of the power splitters were optimized sequentially to alleviate local minima issues. The proposed power splitters have a compact footprint of 12.32 × 5 μm2 and can be fabricated through a CMOS-compatible fabrication process. Two-stage power splitter trees were measured to enhance reliability in an experiment. As a result, the power splitter with a splitting ratio of 1:1:1:1 exhibited an experimentally measured insertion loss below 0.61 dB and an imbalance below 1.01 dB within the bandwidth of 1,518–1,565 nm. Also, the power splitter with a splitting ratio of 2:1:1:2 showed an insertion loss below 0.52 dB and a targeted imbalance below 1.15 dB within the bandwidth of 1,526–1,570 nm. Such inverse-designed power splitters can be an essential part of many large-scale photonic circuits including optical phased arrays, programmable photonics, and photonic computing chips.

Aperiodic Activity Indexes Neural Hyperexcitability in Generalized Epilepsy.

Generalized epilepsy (GE) encompasses a heterogeneous group of hyperexcitability disorders that clinically manifest as seizures. At the whole-brain level, distinct seizure patterns as well as interictal epileptic discharges (IEDs) reflect key signatures of hyperexcitability in magneto- and electroencephalographic (M/EEG) recordings. Moreover, it had been suggested that aperiodic activity, specifically the slope of the 1/ƒx decay function of the power spectrum, might index neural excitability. However, it remained unclear if hyperexcitability as encountered at the cellular level directly translates to putative large-scale excitability signatures, amenable to M/EEG. In order to test whether the power spectrum is altered in hyperexcitable states, we recorded resting-state MEG from male and female GE patients (n = 51; 29 females; 28.82 ± 12.18 years; mean ± SD) and age-matched healthy controls (n = 49; 22 females; 32.10 ± 12.09 years). We parametrized the power spectra using FOOOF ("fitting oscillations and one over f") to separate oscillatory from aperiodic activity to directly test whether aperiodic activity is systematically altered in GE patients. We further identified IEDs to quantify the temporal dynamics of aperiodic activity around overt epileptic activity. The results demonstrate that aperiodic activity indexes hyperexcitability in GE at the whole-brain level, especially during epochs when no IEDs were present (p = 0.0130; d = 0.52). Upon IEDs, large-scale circuits transiently shifted to a less excitable network state (p = 0.001; d = 0.68). In sum, these results uncover that MEG background activity might index hyperexcitability based on the current brain state and does not rely on the presence of epileptic waveforms.

Moment neural network and an efficient numerical method for modeling irregular spiking activity.

Continuous rate-based neural networks have been widely applied to modeling the dynamics of cortical circuits. However, cortical neurons in the brain exhibit irregular spiking activity with complex correlation structures that cannot be captured by mean firing rate alone. To close this gap, we consider a framework for modeling irregular spiking activity, called the moment neural network, which naturally generalizes rate models to second-order moments and can accurately capture the firing statistics of spiking neural networks. We propose an efficient numerical method that allows for rapid evaluation of moment mappings for neuronal activations without solving the underlying Fokker-Planck equation. This allows simulation of coupled interactions of mean firing rate and firing variability of large-scale neural circuits while retaining the advantage of analytical tractability of continuous rate models. We demonstrate how the moment neural network can explain a range of phenomena including diverse Fano factor in networks with quenched disorder and the emergence of irregular oscillatory dynamics in excitation-inhibition networks with delay.

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization

Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The worst degradation collection cost reduction brings an inaccurate training dataset when a machine learning (ML) model is used to fast perform the estimation. Motivated by the fact that there are many similar subcircuits in large-scale analog circuits, in this article we propose Wages to train an ML model on an inaccurate dataset for the worst aging degradation estimation via a domain generalization technique. A sampling-based method on the feature space of the transistor and its neighborhood subcircuit is developed to replace inaccurate labels. A consistent estimation for the worst degradation is enforced to update model parameters. Label updating and model updating are performed alternately to train an ML model on the inaccurate dataset. Experimental results on the very advanced 5 nm technology node show that our Wages can significantly reduce the label collection cost with a negligible estimation error for the worst aging degradations compared to the traditional methods.

A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm

Logic synthesis is a crucial step in integrated circuit design, and power optimization is an indispensable part of this process. However, power optimization for large-scale Mixed Polarity Reed-Muller (MPRM) logic circuits is an NP-hard problem. In this article, we divide Boolean circuits into small-scale circuits based on the idea of divide and conquer using the proposed Dynamic Adaptive Grouping Strategy (DAGS) and the proposed circuit decomposition model (CDM). Each small-scale Boolean circuit is transformed into an MPRM logic circuit by a polarity transformation algorithm. Based on the gate-level integration, we integrate small-scale circuits into an MPRM and Boolean Dual Logic (RBDL) circuit. Furthermore, the power optimization problem of RBDL circuits is a multi-task, multi-extremal, high-dimensional combinatorial optimization problem, for which we propose an Adaptive Multi-task Intelligent Algorithm (AMIA), which includes global task optimization, population reproduction, valuable knowledge transfer (VKT), and local exploration to search for the lowest power for RBDL circuits. Moreover, based on the proposed Fast Power Decomposition Algorithm (FPDA), we proposed a Power Optimization Approach (POA) for an RBDL circuit with the lowest power using the AMIA. Experimental results based on Microelectronics Center of North Carolina (MCNC) Benchmark test circuits demonstrate the effectiveness and superiority of the POA compared to state-of-the-art POAes.

Scalable Fabrication of Large-Scale, 3D, and Stretchable Circuits.

Stretchable electronics have demonstrated excellent potential in wearable healthcare and conformal integration. Achieving the scalable fabrication of stretchable devices with high functional density is the cornerstone to enable the practical applications of stretchable electronics. Here, a comprehensive methodology for realizing large-scale, 3D, and stretchable circuits (3D-LSC) is reported. The soft copper-clad laminate (S-CCL) based on the "cast and cure" process facilitates patterning the planar interconnects with the scale beyond 1 m. With the ability to form through, buried and blind VIAs in the multilayer stack of S-CCLs, high functional density can be achieved by further creating vertical interconnects in stacked S-CCLs. The application of temporary bonding substrate effectively minimizes the misalignments caused by residual strain and thermal strain. 3D-LSC enables the batch production of stretchable skin patches based on five-layer stretchablecircuits, which can serve as a miniaturized system for physiological signals monitoring with wireless power delivery. The fabrications of conformal antenna and stretchable light-emitting diode display further illustrate the potential of 3D-LSC in realizing large-scale stretchable devices.

Site-Selective Synthesis of Bilayer Graphene on Cu Substrates Using Titanium as a Carbon Diffusion Barrier.

Chemical vapor deposition (CVD) is a widely used method for graphene synthesis, but it struggles to produce large-area uniform bilayer graphene (BLG). This study introduces a novel approach to meet the demands of large-scale integrated circuit applications, challenging the conventional reliance on uniform BLG over extensive areas. We developed a unique method involving the direct growth of bilayer graphene arrays (BLGA) on Cu foil substrates using patterned titanium (Ti) as a diffusion barrier. The use of the Ti layer can effectively control carbon atom diffusion through the Cu foil without altering the growth conditions or compromising the graphene quality, thereby showcasing its versatility. The approach allows for targeted BLG growth and achieved a yield of 100% for a 10 × 10 BLG units array. Then a 10 × 10 BLG memristor array was fabricated, and a yield of 96% was achieved. The performances of these devices show good uniformity, evidenced by the set voltages concentrated around 4 V, and a high resistance state (HRS) to low resistance state (LRS) ratio predominantly around 107, reflecting the spatial uniformity of the prepared BLGA. This study provides insight into the BLG growth mechanism and opens new possibilities for BLG-based electronics.

An aging simulation method based on the change of input vector inside the critical path

Abstract With the large-scale expansion and process shrinking of modern integrated circuits, aging has become one of the main factors threatening circuit reliability. To evaluate the impact of aging on circuit life, it is important to investigate aging simulation methods. Aiming at the problem of slow speed and insufficient accuracy of large-scale digital circuit aging simulation methods, a circuit aging simulation method based on the change of input vector inside the critical path (CICP) is proposed in this paper. First, the critical path (CP) with the tightest timing is extracted by static timing analysis (STA), and SPICE simulation is carried out to accurately predict the aging of the CP of the circuit. Second, the aging simulation is carried out considering the change of the internal input vector of the CP. The simulation results show that after changing the internal input signal, the aging path delay increases up to 3.5%.

Beyond earth: Evaluating SiC and GaN as next-generation semiconductors for Venus exploration

Abstract This paper evaluates Silicon Carbide (SiC) and Gallium Nitride (GaN) as potential wide-bandgap semiconductor materials for Venus’ surface exploration. Both materials possess properties advantageous for withstanding Venus’ extreme conditions. Through an in-depth comparison, the study examines stability, energy efficiency, and integration levels of both materials. Although GaN showcases superior electron mobility and potential for high energy efficiency, it confronts challenges in large-scale circuit integration due to its limited wafer size and intricacies in device structure design. Conversely, SiC-based processors have demonstrated operability at high temperatures, with performance comparable to computers used in previous space missions. While neither material currently achieves the processing prowess of past space exploration computers, the study recommends SiC for Venus exploration due to its demonstrated capabilities and higher potential for integration. The paper concludes that optimized SiC processors hold promise for future Venusian surface missions.

Sensation and expectation are embedded in mouse motor cortical activity

During behavior, the motor cortex sends copies of motor-related signals to sensory cortices. Here, we combine closed-loop behavior with large-scale physiology, projection-pattern-specific recordings, and circuit perturbations to show that neurons in mouse secondary motor cortex (M2) encode sensation and are influenced by expectation. When a movement unexpectedly produces a sound, M2 becomes dominated by sound-evoked activity. Sound responses in M2 are inherited partially from the auditory cortex and are routed back to the auditory cortex, providing a path for the reciprocal exchange of sensory-motor information during behavior. When the acoustic consequences of a movement become predictable, M2 responses to self-generated sounds are selectively gated off. These changes in single-cell responses are reflected in population dynamics, which are influenced by both sensation and expectation. Together, these findings reveal the embedding of sensory and expectation signals in motor cortical activity.

Robust Quantum Gates against Correlated Noise in Integrated Quantum Chips.

As quantum circuits become more integrated and complex, additional error sources that were previously insignificant start to emerge. Consequently, the fidelity of quantum gates benchmarked under pristine conditions falls short of predicting their performance in realistic circuits. To overcome this problem, we must improve their robustness against pertinent error models besides isolated fidelity. Here, we report the experimental realization of robust quantum gates in superconducting quantum circuits based on a geometric framework for diagnosing and correcting various gate errors. Using quantum process tomography and randomized benchmarking, we demonstrate robust single-qubit gates against quasistatic noise and spatially correlated noise in a broad range of strengths, which are common sources of coherent errors in large-scale quantum circuits. We also apply our method to nonstatic noises and to realize robust two-qubit gates. Our Letter provides a versatile toolbox for achieving noise-resilient complex quantum circuits.