Large Random Access Memory Research Articles

Processing Next-Generation Mass Spectrometry Imaging Data: Principal Component Analysis at Scale.

Mass spectrometry imaging (MSI) is constantly improving in spatial resolving power, throughput and mass resolution. Although beneficial, these improvements increase data set size and content. The larger data requires correspondingly fast computer-based analyses. However, these analyses often do not scale well with increased data size. Principal component analysis (PCA) is an important analytical tool commonly used with MSI data; however, most PCA algorithms load and process the entire data set within random access memory (RAM) which is most often insufficient for large data sets. PCA algorithms that use less RAM than the data set exist but are usually much slower or sacrifice precision and are rarely used for MSI data processing. Incremental PCA (IPCA) is an alternative algorithm that avoids large RAM allocations while also preserving speed and analytical precision. Here, we demonstrate and benchmark the use of differing implementations of IPCA, PCA, and commercial software on large and often complex MSI data sets. We show that using an already-published Python-based IPCA algorithm, IPCA can be successfully applied to MSI data sets too large to fit with RAM. Furthermore, our benchmarks demonstrate that, contrary to expectations, IPCA is faster than all other tested PCA implementations on all large data sets that can be directly compared.

Ultra8T: A sub-threshold 8T SRAM with leakage detection

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 μs read delay, and the minimum energy required is 1.69 pJ at 0.4 V

Effect of temperature on structural, dynamical, and electronic properties of Sc2Te3 from first-principles calculations.

The compounds Sc2Te3 and Sb2Te3 have the same crystal structure. Ge-Sb-Te alloys are also the most common prototype phase change memory (PCM) compounds in the GeTe-Sb2Te3 pseudo-binary combination. Recently, alloying Sc atoms into Sb2Te3 has enabled sub-nanosecond switching in large conventional phase-change random access memory (PCRAM) devices. However, prior study on the electronic structure and dynamic properties of the Sc2Te3 system is very limited. In this work, we investigate the effect of temperature on the structural, dynamic, and electronic properties of the Sc2Te3 compound through ab initio molecular dynamics simulations. We show that the distorted-octahedral clusters are connected by four-fold rings even at higher temperatures. Moreover, our results clearly illustrate a liquid-to-glass transition temperature, which is between approximately 773 K and 950 K. The effect of temperature changes on the electronic properties of the system manifests as a metal-to-semiconductor transition. The band gap obtained using the mBJLDA functional is twice the value obtained using the PBE functional. Our studies provide useful insight into the local structure and dynamic and electronic properties of the Sc2Te3 system at the atomic level. We hope that this work could stimulate more theoretical work on the development of cache-type phase-change memory and broaden its application in the field of PCM.

Validation of android-based mobile application for retrieving network signal level

<p><span>In recent years, the evolvement of mobile devices which perform sophisticated functions have been on the rise. Mobile applications which solved engineering challenges are now available due to the high computational capabilities, large random access memory and storage location of the mobile devices. An Android application called signal detect, which measures network signal strength value from 2G-4G received on an android mobile device has been developed using android app development environment called Android studio. Validation becomes necessary because different readings were obtained on smartphones with different specifications. Two validation techniques were used to validate the data obtained. To know the efficiency of the application; a field strength meter was used to compare the readings received on the mobile device with the meter. It was observed that there is a time lag on the received values of the mobile device to the field strength meter. Therefore, a moving average technique was used to correlate the two data which increased the correlation coefficient to about 0.85.</span></p>

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z2-FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state ( ${D}_{\text {it}}$ ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.

Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application

Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

SMFrWF: Segmented Modified Fractional Wavelet Filter: Fast Low-Memory Discrete Wavelet Transform (DWT)

This paper proposes a novel algorithm to compute the 2-D discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost visual sensor and Internet of Things (IoT) nodes. The main advantages of the proposed segmented modified fractional wavelet filter (SMFrWF) are reduced computation (time) complexity and energy consumption compared to the state-of-the-art low-memory 2-D DWT computation methods. In particular, the conventional convolution-based DWT is very fast but requires large random access memory (RAM), as the entire image needs to be in the system memory. The fractional wavelet filter (FrWF) requires only a small RAM but has high complexity due to multiple readings of image lines. The proposed SMFrWF avoids the multiple readings of image lines, thus reducing the memory read access time and, thereby, the complexity. We evaluated the proposed SMFrWF through MATLAB simulations with 70 popular gray-scale test images of dimensions ranging from $256 \times 256$ up to $8192 \times 8192$ pixels. The results show that for images of size $2048\times 2048$ pixels, the proposed SMFrWF (with four segments per line) has 16.8% and 53.6% lower time complexities than the conventional DWT and FrWF, respectively. The proposed SMFrWF has also been modeled in a hardware description language (HDL) and implemented on an Artix-7 field-programmable gate array (FPGA) platform to evaluate the hardware performance. We observed that the proposed SMFrWF has 65% lower energy consumption than the FrWF (both implemented on the same board). Thus, the proposed SMFrWF appears suitable for computing the wavelet transform coefficients of HR images on low-cost visual sensors and IoT platforms.

Design of CMOS Compatible, High‐Speed, Highly‐Stable Complementary Switching with Multilevel Operation in 3D Vertically Stacked Novel HfO2/Al2O3/TiOx (HAT) RRAM

AbstractComplementary resistive switching (CRS) is a suitable approach to minimize the sneak leakage paths through a large resistive random access memory (RRAM) array. Here, an effective CRS design with a HfO2/Al2O3/TiOx (HAT) trilayer structure integrated in a 3D vertically stacked RRAM array is reported. The design shows voltage‐controlled resistive switching and CRS performance with multilevel operations. High‐speed switching is observed with the HAT design. The device shows SET and the RESET transitions with speeds of −3.5 V@30 ns and +3.8 V@150 ns, respectively. As well as with the DC measurements, the CRS switching is achieved under AC switching dynamics measurement. Maintaining the same applied pulse polarity, the lower amplitude can switch the device to the SET and the higher amplitude can switch it to the RESET. A highly nonlinear (nonlinearity >102) CRS is obtained at a high temperature of 150 °C. In the HAT devices, the origin of CRS is due to the anionic redistribution in HfO2 and TiOx layers, leaving Al2O3 as tunnel barrier. The achievements reported here indicate the applicability of the HAT design for future high‐speed high‐density applications.

A Novel Architecture of Large Hybrid Cache With Reduced Energy

Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells’ value but still cost high write energy. In this paper, we first design a large hybrid cache architecture with the DRAM region and the STT-RAM region to reduce the high static energy of DRAM cache. The selective write back to row buffer and selective write back to cell array optimizations are proposed to reduce high write energy of the STT-RAM region by removing the unnecessary bit-writes. Furthermore, we propose reuse distance-oriented data movement to reduce write operations in the STT-RAM region. Finally, we propose a novel tag design for the hybrid cache by moving all tag arrays to the STT-RAM region. The SPEC CPU2006 benchmarks show an average 28.3% energy reduction and 6.7% performance improvement for the write optimizations and 7.3% energy savings and 27.5% instructions per cycle speedups for the proposed tag design.

Statistical analysis of the correlations between cell performance and its initial states in contact resistive random access memory cells

Variability has been one of the critical challenges in the implementation of large resistive random access memory (RRAM) arrays. Wide variations in set/reset, read and cycling characteristics can significantly reduce the design margin and feasibility of a memory array. Predicting the characteristics of RRAM cells is constructive to provide insights and to adjust the memory operations accordingly. In this study, a strong correlation between the cell performance and its initial state is found in contact RRAM (CRRAM) cells by 28 nm CMOS logic technology. Furthermore, a verify-reset operation is proposed to identify the type of conductive filament (CF) in a cell. Distinctive CRRAM characteristics are found to be linked directly to initial CFs, enabling preliminary screening and adaptive resets to address the large variability problems in sizable CRRAM arrays.

A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array

The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 μA due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.

Multiparadigm Parallel Acceleration for Reservoir Simulation

Summary With the advent of the multicore central-processing unit (CPU), today's commodity PC clusters are effectively a collection of interconnected parallel computers, each with multiple multicore CPUs and large shared random access memory (RAM), connected together by means of high-speed networks. Each computer, referred to as a compute node, is a powerful parallel computer on its own. Each compute node can be equipped further with acceleration devices such as the general-purpose graphical processing unit (GPGPU) to further speed up computational-intensive portions of the simulator. Reservoir-simulation methods that can exploit this heterogeneous hardware system can be used to solve very-large-scale reservoir-simulation models and run significantly faster than conventional simulators. Because typical PC clusters are essentially distributed share-memory computers, this suggests that the use of the mixed-paradigm parallelism (distributed-shared memory), such as message-passing interface and open multiprocessing (MPI-OMP), should work well for computational efficiency and memory use. In this work, we compare and contrast the single-paradigm programming models, MPI or OMP, with the mixed paradigm, MPI-OMP, programming model for a class of solver method that is suited for the different modes of parallelism. The results showed that the distributed memory (MPI-only) model has superior multicompute-node scalability, whereas the shared memory (OMP-only) model has superior parallel performance on a single compute node. The mixed MPI-OMP model and OMP-only model are more memory-efficient for the multicore architecture than the MPI-only model because they require less or no halo-cell storage for the subdomains. To exploit the fine-grain shared memory parallelism available on the GPGPU architecture, algorithms should be suited to the single-instruction multiple-data (SIMD) parallelism, and any recursive operations are serialized. In addition, solver methods and data store need to be reworked to coalesce memory access and to avoid shared memory-bank conflicts. Wherever possible, the cost of data transfer through the peripheral component interconnect express (PCIe) bus between the CPU and GPGPU needs to be hidden by means of asynchronous communication. We applied multiparadigm parallelism to accelerate compositional reservoir simulation on a GPGPU-equipped PC cluster. On a dual-CPU-dual-GPGPU compute node, the parallelized solver running on the dual-GPGPU Fermi M2090Q achieved up to 19 times speedup over the serial CPU (1-core) results and up to 3.7 times speedup over the parallel dual-CPU X5675 results in a mixed MPI + OMP paradigm for a 1.728-million-cell compositional model. Parallel performance shows a strong dependency on the subdomain sizes. Parallel CPU solve has a higher performance for smaller domain partitions, whereas GPGPU solve requires large partitions for each chip for good parallel performance. This is related to improved cache efficiency on the CPU for small subdomains and the loading requirement for massive parallelism on the GPGPU. Therefore, for a given model, the multinode parallel performance decreases for the GPGPU relative to the CPU as the model is further subdivided into smaller subdomains to be solved on more compute nodes. To illustrate this, a modified SPE5 (Killough and Kossack 1987) model with various grid dimensions was run to generate comparative results. Parallel performances for three field compositional models of various sizes and dimensions are included to further elucidate and contrast CPU-GPGPU single-node and multiple-node performances. A PC cluster with the Tesla M2070Q GPGPU and the 6-core Xeon X5675 Westmere was used to produce the majority of the reported results. Another PC cluster with the Tesla M2090Q GPGPU was available for some cases, and the results are reported for the modified SPE5 (Killough and Kossack 1987) problems for comparison.

E-Passport Threats

The International Civil Aviation Organization (ICAO) standardized e-passports by specifying how to implement and protect machine-readable travel documents. E-passports have embedded contactless chips that can be read by radio from tip to a few centimeters away. The ICAO chose this technology over magnetic strips and 2D barcodes because it provides reliable connection, large memory capacity, random access, and rewritable memory. As with many other RFID devices, the chip in e-passports uses a 32-bit number for collision avoidance. Every country maintains its own public-key infrastructure (PKI) and exchanges root certificates with other countries via diplomatic means. Agencies issuing e-passports have their own public keys and certificates from the PKI. In this way, a passive authentication mechanism verifies every data group's digest. With today's e-passports, private information is limited to the MRZ and a digital picture, but the goal is to eventually add more biometrics at some point, along with a digitized handwritten signature.

Estimation of thermal durability and intrinsic critical currents of magnetization switching for spin-transfer based magnetic random access memory

To realize a large capacity magnetic random access memory (MRAM) that uses spin-transfer switching for writing, it is essential to evaluate thermal durability and intrinsic critical currents correctly. Here, we examined the theoretically predicted logarithmic relationship between critical currents of spin-transfer switching and duration of injected pulsed currents using giant magnetoresistive (GMR) samples with different magnetic materials, e.g., Co, Co–Fe25, and CoFeB. This relationship was verified for the samples by giving reasonable thermal-durability coefficients and intrinsic critical currents as fitting parameters. We found that thermal durability was underestimated when an effective magnetic field acted on magnetic memory cells antiparallel to their magnetization. We then experimentally demonstrated that thermal assistance in spin-transfer switching decreased with increasing thermal durability.

(Ba,Sr)TiO 3 thin films for ultra large scale dynamic random access memory. : A review on the process integration

Integration processes of the (Ba,Sr)TiO 3 (BST) capacitors for the next-generation dynamic random access memories (DRAMs) are reviewed. Various integration schemes utilizing different processes, different electrode materials and structures are reviewed from the point of view of the mass-production compatible process. Integration issues, mostly related to the electrode and the barrier material and their fabrication techniques, are described. The current status and the problems of the two most viable techniques for the BST deposition, sputtering and metal-organic chemical vapor deposition (MOCVD), are comparatively described. Plate electrode technologies with the back-end processing issues are also briefly described, and some valuable experimental results are presented to show the feasibility of the BST capacitor.

A fast algorithm for computing minimum cross-entropy positive time-frequency distributions

An algorithm for obtaining nonnegative, joint time-frequency distributions Q(t, f) satisfying the univariate marginals |s(t)|/sup 2/ and |S(f)|/sup 2/ is presented and applied. The advantage of the algorithm is that large time series records can be processed without the need for large random access memory (RAM) and central processing unit (CPU) time. This algorithm is based on the Loughlin et al. (1992) method for synthesizing positive distributions using the principle of minimum cross-entropy. The nonnegative distributions with the correct marginals that are obtained using this approach are density functions as proposed by Cohen and Zaparovanny (1980) and Cohen and Posch (1985). Three examples are presented: the first is a nonlinear frequency modulation (FM) sweep signal (simulated data); the second and third are of physical systems (real data). The second example is the signal for the acoustic scattering response of an elastic cylindrical shell structure. The third example is of an acoustic transient signal from an underwater vehicle. Example one contains 7500 data points, example two contains 256 data points, and example three contains in excess of 30000 data points. The RAM requirements using the original Loughlin et al. algorithm for a 7500 data point signal is 240 mega bytes and for a 30000 data point signal is 3.5 billion bytes. The new algorithm reduces the 240 mega byte requirement to 1 mega byte and the 3.5 billion byte requirement to 4 million bytes. Furthermore, the fast algorithm runs 240 times faster for the 7500 data point signal and 3000 times faster for the 30000 data point signal as compared with the original Loughlin et al. algorithm.

Optoelectronic-cache memory system architecture

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.

Estimation of the LET threshold of single event upset of microelectronics in experiments with Cf-252

A method is proposed for analyzing single event upsets (SEU) in large scale integration circuits or random access memory (RAM) when exposed to Cf-252 fission fragments. The method makes it possible to find the RAM linear energy transfer (LET) threshold to be used for estimation of RAM SEU rates in space. The method is illustrated by analyzing experimental data for the 2 × 8 kbit CMOS/bulk RAM.

New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement

Two approaches for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares are presented. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yield at manufacturing and production times. The first approach, the faulty line covering technique, is a refinement of the fault-driven approach. This approach finds the optimal repair solution within a smaller number of iterations than the fault-driven algorithm. The second approach exploits a heuristic criterion in the generation of the repair solution. This heuristic criterion permits a fast repair. The criterion is based on the calculation of efficient coefficients for the rows and columns of the memory. Simulation results are presented. Comparison of the proposed heuristic approaches with the fully exhaustive approach shows that repair can be accomplished in most cases. A considerable reduction in processing and complexity (number of records generated in the repair process for finding the optimal repair solution) is accomplished. >

Imaging cytoplasmic free calcium in histamine stimulated endothelial cells and in fMet-Leu-Phe stimulated neutrophils

Intracellular free [Ca 2+] ([Ca 2+] i) was imaged in Fura-2 loaded human umbilical vein endothelial cells, using dual excitation light, an inverted epifluorescence microscope and a silicon intensified target camera. Oscillations of [Ca 2+] i were induced in these cells by 0.5 μM histamine. Because the image processor contained a large random access memory of 32 Mbyte, it was possible to follow these oscillations over a period of several minutes with a time resolution of approximately 2 s. Plots of the variation of average [Ca 2+] i measured from these images in neighbouring cells showed that not only were the oscillations asynchronous but also that they occurred at different frequencies. This indicates that there is no strong coupling of [Ca 2+] i in adjacent endothelial cells. The rise in [Ca 2+] i stimulated by 0.5 μM histamine was qualitatively imaged at 80 ms intervais by recording images at 380 nm only. [Ca 2+] i-independent variations in image intensity were removed by ratioing these images against a 380 nm image obtained before the stimulation by histamine. Such images revealed that [Ca 2+] i rises first locally and then propagates across the cell at approximately 50 μm.s −1. Neutrophils were imaged following stimulation by fMet-Leu-Phe, also with a time resolution of 2 s. Three responses were determined from the images: (a) the rise in [Ca 2+] i; (b) the cell spreading; and (c) the chemokinesis. Measuring these responses in single cells clearly showed the temporal relationships with the responses occurring in the order listed above.