Large Process Variations Research Articles

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network

Optical proximity correction (OPC) in modern design closures has become extremely expensive and challenging. Conventional model-based OPC encounters performance degradation and large process variation, while aggressive approach, such as inverse lithography technology (ILT), suffers from large computational overhead for both mask optimization and mask writing processes. In this article, we developed Neural-ILT, an end-to-end learning-based OPC framework, which literally conducts mask prediction and ILT correction for a given layout in a single neural network, with the objectives of: 1) mask printability enhancement; 2) mask complexity optimization; and 3) flow acceleration. A domain-specific model pretraining recipe, which introduces the domain knowledge of lithography system, is proposed to help Neural-ILT achieving faster and better convergence. Quantitative results show that compared to the state-of-the-art (SOTA) learning-based OPC solutions and conventional OPC flows, Neural-ILT can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$30\times $ </tex-math></inline-formula> turnaround time (TAT) speedup and the best mask printability with relatively lower mask complexity. Based on the developed infrastructure, we further investigated the feasibility of handling multiple mask optimization tasks for different datasets within a common Neural-ILT platform. We believe this work could bridge well-developed deep learning toolkits to GPU-based high-performance lithographic computations to achieve groundbreaking performance boosting on various computational lithography-related tasks.

Single-Branch Wide-Swing-Cascode Subthreshold GaN Monolithic Voltage Reference

A voltage reference generator in GaN IC technology for smart power applications is described, analyzed, and simulated. A straightforward design procedure is also highlighted. Compared to previous low-power monolithic solutions, the proposed one is based on a single branch and on transistors operating in a subthreshold. The circuit provides a nearly 2.7 V reference voltage under 4 V to 24 V supply at room temperature and with typical transistor models. The circuit exhibits a good robustness against large process variations and improves line regulation (0.105 %V) together with a reduction in area occupation (0.05 mm2), with a reduced current consumption of 2.7 µA (5 µA) in the typical (worst) case, independent of supply. The untrimmed temperature coefficient is 200 ppm/°C.

Continuous manufacturing process monitoring of pharmaceutical solid dosage form: A case study

Continuous Manufacturing (CM) of pharmaceutical drug products is a rather new approach within the pharmaceutical industry. In the presented paper, a GMP continuous wet granulation line used for clinical production of solid dosage forms was investigated with a thorough monitoring strategy regarding process performance and robustness. The line was composed of the subsequent continuous unit operations feeding – twin-screw wet-granulation – fluid-bed drying – sieving and tableting; the formulation of a new pharmaceutical entity in development was selected for this study. In detail, a Design of Experiments (DoE) was used to evaluate the impact of the three main factors (amount of water, filling rate, and shear force in twin-screw granulator) on the tablet quality. The process was monitored via in-process control (IPC) tests (e.g. weight, hardness, disintegration, and loss-on-drying), Process Analytical Technologies (PAT), and through the analysis of the process parameters (multivariate process control). The tested formulation was very robust to the large process variation of the DoE: all IPC results were in specification, the PAT probes provided stable results for the content uniformity and no critical variations can be detected in the process parameters. An adequate monitoring strategy was presented and the robustness of the process with one formulation has been demonstrated. In summary, this continuous process in combination with smart formulation development allows the robust production of constant quality tablets. The synergy between PAT, process data science and IPC creates an adequate monitoring framework of the continuous manufacturing line.

Variability Modeling for Printed Inorganic Electrolyte-Gated Transistors and Circuits

Electrolyte-gated field-effect transistor technology is an attractive candidate for printed low-power electronics due to its high field-effect mobility and extremely low-voltage operation. Relying on an additive process, inkjet-printed devices display large process variations due to ink-substrate interactions, sensitivity to environmental conditions, such as temperature and humidity, as well as intrinsic variations of the ink. All of these sources of variations may display themselves in non-Gaussian distributions as suggested by our experiments. In this paper, we therefore propose a generic methodology for variability modeling of printed transistors, based on the Gaussian mixture model, which can be used to model any arbitrary distribution of the transistor model parameters. The proposed methodology was tested on two different data sets and has been used to predict the behavior of a measured printed security circuit as well as transistor dc characteristics.

Scalable Test Generation for Trojan Detection Using Side Channel Analysis

Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this paper, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of multiple excitation of rare switching (MERS), that can significantly increase Trojan detection sensitivity. This paper makes several important contributions: 1) it presents in detail a scalable statistical test generation method, which can generate high-quality test set for creating high relative activity in arbitrary Trojan instances; 2) it analyzes the effectiveness of generated test set in terms of Trojan coverage; and 3) it describes two judicious reordering methods that can further tune the test set and greatly improve the side channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using side-channel analysis.

CNFET-Based High Throughput SIMD Architecture

Carbon nanotube field effect transistor (CNFET), using the carbon nanotubes (CNTs) as the material for conducting, is a promising alternative of CMOS technology to overcome the “power wall” issue. Recently, a microprocessor solely based on CNFETs was fabricated and demonstrated, which is a big step forward to the industrial practice. However, CNFETs are inherently subject to much larger process variation or manufacturing defects; thereby it may cause significant design cost to build high performance processors. This is exacerbated in the large register file (RF) architectures widely used in single instruction multiple data (SIMD) architectures, e.g., general public utilities style processors, where the number of critical paths are multiplied by the SIMD width and thread count. In this paper, we seek cost-effective approaches to address the issues by judiciously exploiting the strong asymmetric spatial correlation in the variation unique to the CNFET fabrication process. This paper presents a microarchitectural model to characterize CNFET delay variation and malfunction, under which we show that the RF organizations coupled with the architectural schemes are critical to the performance and power consumption of the SIMD processor. Therefore, we propose several architectural techniques to mitigate the performance degradation and the impact of CNT metallization, leveraging the distinctive CNFET characteristics and the unique features in the SIMD processors. Experimental results verify the effectiveness of the proposed techniques and demonstrate the great opportunity offered by this new device technology.

Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs

A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phase-locked loops (PLLs). A passive RC filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is −79 dBc for an oscillator gain of 0.1 GHz/V and −46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integer-N PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with $320~\mu \text{W}$ of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of −53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration.

A —244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique

This paper proposes a cascaded fractional-N phase-locked loop (PLL) based on a high-frequency piezoelectric resonator (PZR). Sub-ppb-order frequency resolution is achieved by a channel adjustment technique. Besides its small form factor, a high- ${Q}$ PZR at gigahertz frequencies realizes a very low phase-noise synthesizer for RF applications. However, three fundamental issues remain to be solved: the narrow tuning range and large process variation of PZR-based oscillators, the low-frequency resolution of a PLL referenced to gigahertz-order frequencies, and the undesirable harmonic oscillation caused by the inductance of the CMOS-PZR bonding wire. To overcome these issues, we propose a channel-adjusting technique (CAT) that adaptively sets the division ratio of two PLLs to maintain constant output frequency of the second PLL while varying the PZR oscillator frequency, hence permitting the narrow tuning range and wide process variation of the PZR oscillator. The first PLL in our PLL architecture determines the output frequency resolution and the second reduces the power consumption of the delta–sigma modulator. We also suppress the harmonic oscillations in the PZR oscillator. The prototype PLL is fabricated in a 65-nm CMOS and achieves an 8.484–8.912-GHz output, 180-fs rms jitter, and −244-dB FOM while consuming 12.7-mW power. We developed a cascaded fractional-N PLL based on a high-frequency PZR with a sub-ppb-order CAT, which overcomes the narrow tuning range problem in gigahertz PZRs. A prototype PLL fabricated in a 65-nm CMOS consumed 12.7 mWand output 8.484–8.912 GHz with 180-fs rms jitter.

ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM

Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.

One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits

A calibration mechanism is often desired in analog/RF circuits that are designed in advance process nodes which exhibit large process variation, so as to recover yield loss and obtain the best possible trade-off between performances. In this paper, we present a calibration approach based on embedded sensors that has several appealing attributes. Specifically, it is virtually applicable to any circuit, the calibration mechanism is totally non-intrusive and, thereby, it does not degrade the performances of the circuit, and the calibration is performed in one-shot requiring a single test step, thus the calibration time is kept at a minimum. The proposed calibration approach is demonstrated experimentally on a 65 nm RF power amplifier based on fabricated chips from two corner wafers and a typical wafer.

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy.

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.

SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection

Counterfeit chips in a supply chain have emerged as a major security concern in the semiconductor industry with serious potential consequences (such as performance degradation, revenue, and reputation loss). With rising incidences of this attack, wide-spread effort has been made in both industry and academia to develop effective countermeasures. However, existing solutions to protect against these attacks suffer from both robustness issue (in terms of detecting chips with minor functional/structural deviations) as well as design/area overhead and test cost. In addition, they cannot reliably detect different forms of cloning attacks. In this paper, we propose a novel characterization method to identify counterfeit chips - in particular, the cloned ones - based on extraction of scan path delay signatures of a chip. It uses the scan chain, a prevalent design-for-testability structure, to create a robust authentication signature. The proposed approach has two major advantages: 1) it comes at virtually zero design and hardware overhead, since it does not require any additional embedded structure; and 2) it alleviates the design house from characterizing each manufactured chip instance, thus mitigating test cost. In addition, a novel and practical method based on clock phase sweep is proposed to measure delay of short scan paths with high resolution. Using Monte Carlo simulation on the layouts of two ISCAS-89 benchmarks at 45-nm CMOS process, we observe that over 99% of counterfeit chips can be reliably identified even under large process variations. Effectiveness of the approach is also validated with delay measurements in field programmable gate array chips.

Complex permittivity extraction from PCB stripline measurement using recessed probe launch

A method to extract the complex permittivity of a dielectric material in a PCB is presented. The recessed probe launch allows striplines to be measured without the need of via transitions that are subject to large process variations. After pad parasitics are de-embedded using the two-line method, the complex permittivity of the dielectric is calculated from 20 MHz to 5 GHz using closed-form equations. Internal inductance is taken into account to prevent overestimation of the permittivity at low frequency.

Pressure Sensor Interface Circuit Based on Silicon Carbide Electronics for Harsh Environment Operation

Pressure sensing in harsh environments poses many difficulties. The major challenge is implementing a sensor interface circuit capable of operation at high temperatures ( 300°C) for extended periods of time. Conventional, siliconbasedelectronics are not suitable for operation in such conditions due to their sizable leakage currents and junction instability. Inthis work, a wireless solution based on silicon carbide electronics is presented. The proposed solution follows a simple design procedure and exhibits robustness to the large process variations typically associated with silicon carbide technology.

Detecting Hardware Trojan through Time Domain Constrained Estimator Based Unified Subspace Technique

SUMMARY Hardware Trojan (HT) has emerged as an impending security threat to hardware systems. However, conventional functional tests fail to detect HT since Trojans are triggered by rare events. Most of the existing side-channel based HT detection techniques just simply compare and analyze circuit’s parameters and offer no signal calibration or error correction properties, so they suffer from the challenge and interference of large process variations (PV) and noises in modern nanotechnology which can completely mask Trojan’s contribution to the circuit. This paper presents a novel HT detection method based on subspace technique which can detect tiny HT characteristics under large PV and noises. First, we formulate the HT detection problem as a weak signal detection problem, and then we model it as a feature extraction model. After that, we propose a novel subspace HT detection technique based on time domain constrained estimator. It is proved that we can distinguish the weak HT from variations and noises through particular subspace projections and reconstructed clean signal analysis. The reconstructed clean signal of the proposed algorithm can also be used for accurate parameter estimation of circuits, e.g. power estimation. The proposed technique is a general method for related HT detection schemes to eliminate noises and PV. Both simulations on benchmarks and hardware implementation validations on FPGA boards show the effectiveness and high sensitivity of the new HT detection technique.

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis

Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Sidechannel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However, these techniques suffer from decreased sensitivity toward small Trojans, especially because of the large process variations present in modern nanometer technologies. In this paper, we propose a novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach. We use the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise. We propose a vector generation approach and several design/test techniques to improve the detection sensitivity. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit advanced encryption standard (AES) cipher, show a detection resolution of 1.12 percent amidst ±20 percent parameter variations. The approach is also validated with experimental results. Finally, the use of a combined side-channel analysis and logic testing approach is shown to provide high overall detection coverage for hardware Trojan circuits of varying types and sizes.

Large earthquake rupture process variations on the Middle America megathrust

The megathrust fault between the underthrusting Cocos plate and overriding Caribbean plate recently experienced three large ruptures: the August 27, 2012 (Mw 7.3) El Salvador; September 5, 2012 (Mw 7.6) Costa Rica; and November 7, 2012 (Mw 7.4) Guatemala earthquakes. All three events involve shallow-dipping thrust faulting on the plate boundary, but they had variable rupture processes. The El Salvador earthquake ruptured from about 4 to 20 km depth, with a relatively large centroid time of ∼19 s, low seismic moment-scaled energy release, and a depleted teleseismic short-period source spectrum similar to that of the September 2, 1992 (Mw 7.6) Nicaragua tsunami earthquake that ruptured the adjacent shallow portion of the plate boundary. The Costa Rica and Guatemala earthquakes had large slip in the depth range 15 to 30 km, and more typical teleseismic source spectra. Regional seismic recordings have higher short-period energy levels for the Costa Rica event relative to the El Salvador event, consistent with the teleseismic observations. A broadband regional waveform template correlation analysis is applied to categorize the focal mechanisms for larger aftershocks of the three events. Modeling of regional wave spectral ratios for clustered events with similar mechanisms indicates that interplate thrust events have corner frequencies, normalized by a reference model, that increase down-dip from anomalously low values near the Middle America trench. Relatively high corner frequencies are found for thrust events near Costa Rica; thus, variations along strike of the trench may also be important. Geodetic observations indicate trench-parallel motion of a forearc sliver extending from Costa Rica to Guatemala, and low seismic coupling on the megathrust has been inferred from a lack of boundary-perpendicular strain accumulation. The slip distributions and seismic radiation from the large regional thrust events indicate relatively strong seismic coupling near Nicoya, Costa Rica, patchy zones of strong seismic coupling in the shallowest megathrust region along Nicaragua and El Salvador, and small deeper patchy zones of strong seismic coupling near Guatemala, which can be reconciled with the geodetic observations as long as the strong coupling is limited to a small fraction of the megathrust area.

Insights into the Black Liquor Falling Film Evaporation: A Predictive Model of Heat and Mass Transfer

A model of a black liquor falling film evaporator was developed based on the calculation of local heat transfer coefficients and the surface heat flux integration. The insight into the heat flux profile showed that the commonplace approach based on global overall heat transfer coefficients for estimating the heat flux might not always be satisfactory because it relies on the use of a specific industrial control strategy. The insight into the heat exchange process can be efficiently used to estimate the response of an existing train to small or large process variations or modifications in the control strategy. The model can easily be implemented in an evaporation train simulation along with the common industrial control strategy or a new control strategy.

Process-Variation and Temperature Aware SoC Test Scheduling Technique

High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC’02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.