Abstract
Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.
Highlights
Continuous scaling down of the complementary metal oxide semiconductor (CMOS)technology node drives high power issues due to the increasing leakage currents [1] and large data traffic [2]
PMA‐Magnetic tunnel junction (MTJ) including device deposition, annealing for material crystallization and nanopillar etching; including device deposition, annealing for material crystallization and nanopillar etching; in Section 3, in Section 3, time-dependent dielectric breakdown (TDDB) failures will be analyzed and at last we propose some solutions to tolerate the TDDB failures will be analyzed and at last we propose some solutions to tolerate the failures from the failures from the circuit and system functional errors
We identified thatthis thepaper interfacial is extremely to theorigin nanofabrication and
Summary
Continuous scaling down of the complementary metal oxide semiconductor (CMOS)technology node drives high power issues due to the increasing leakage currents [1] and large data traffic [2]. The first generation of STT-MRAM is based on in-plane magnetic anisotropy, which needs the shape of MTJ nanopillar to be in ellipse or rectangular shape to obtain a high thermal energy barrier for data storage [8,9]. Synthetic antiferromagnetic (SAF) pinned layers are commonly included into PMA‐MTJ ferromagnetic layer, for the interface CoFeB/MgO, the origin oftoPMA is the attributed toasthe hybridization by using periodic ultra‐thin multilayers, in order reduce offset field, well as between the iron 3d oxygen. (tThe promise of PMA-MTJ for high-density memory needs the nanopillar size smaller than nanopillar size smaller than 40the nmoxide [20,21], for this purpose, the as oxide barrier should the be resistance as thin as 40 nm [20,21], for this purpose, barrier should be as thin possible to reduce possible to reduce the resistance area product (RA).
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
