Large Negative Threshold Voltage Research Articles

Cryogenic-temperature investigation of negative bias stress inducing threshold voltage instabilities on 4H-SiC MOSFETs

We investigate the effect of Negative-Bias-Temperature-Instability on 4H-Silicon Carbide MOSFETs at room and cryogenic temperature and found a large negative threshold voltage shift at T < 250 K. For T < 140 K, both capture and emission follow an almost ideal exponential transient. Cryogenic temperatures reveal fast interface traps, otherwise difficult to probe at relatively high temperatures; we attribute the threshold voltage shift to a high density of hole traps located: 1) close to the SiC valence band and able to emit within the measurement time window; 2) above the SiC valence band, responsible of the slow transient at low temperature. Finally, the extraction of the emission time constant via Capture Emission Time map analysis allowed to extract the activation energy of mechanism 2 (82 meV).

Decoder-Type Scan Driver Suitable for Flexible and Stretchable Displays

The integration of a scan drive circuit is required for flexible and stretchable displays because a rigid scan driver IC is not flexible and stretchable. In this study, decoder-type scan drivers were developed using amorphous IGZO thin-film transistors for both depletion and enhancement mode TFTs. Simulations and measurements show that the proposed decoder-type scan driver operates well for both the enhancement and depletion-mode TFTs without error. The measurement results show that the proposed circuit provides scan pulses well, even with depletion-mode TFTs with a large negative threshold voltage of around −25 V.

High Annealing Stability of InAlZnO Nanofiber Field-Effect Transistors with Improved Morphology by Al Doping.

In2O3 nanofibers usually suffer a high off-current and consequent low on/off current ratio, as well as a large negative threshold voltage (Vth). Furthermore, regarding Zn doped binary-cation In2O3 nanofibers, severe thermal diffusion of Zn elements can result in deteriorated electrical performance when annealed at high temperature. Here, we applied an electrospinning technique to obtain ternary-cation IAZO nanofibers with controllable Vth and chemical stoichiometry. The presence of the Al element in IAZO nanofibers can lead to more superior microstructure with improved uniformity, lower surface defect, and superior metal-oxide-metal lattice at high annealing temperature. Consequently, our Al-doped ternary-cation IAZO devices exhibited an improved on/off current ratio of 107 and a high electron mobility of ∼10 cm2 V-1 s-1. Moreover, the electron mobility can be increased to 30 cm2 V-1 s-1 in our low-voltage operated FETs with high-k AlOx as the dielectric layer, which can be envisioned to exhibit vast implications for high-performance transparent electronics.

High-performance field effect transistors based on large ratio metal (Al、Ga、Cr) doped In2O3 nanofibers

Indium oxide nanofibers (In2O3 NFs) are considered to be one of the possible channel materials for future electronic devices, however, these NFs devices suffer from low on/off current ratio (Ion/Ioff), large negative threshold voltage (VTH), and high leakage current due to the excess carriers in NFs. A facile one-step electrospinning technique is employed to synthesize metal element (aluminum (Al), chromium (Cr) or gallium (Ga)) highly-doped In2O3 NFs to both improve the electrical performance of the NFs field effect transistors (FETs) and reduce the consumption of indium. The devices exhibit optimal performance at 10 mol% doping concentration (Al, Cr and Ga): small and positive VTH (<6.0 V), large Ion/Ioff (∼108), high saturation current (∼10−4 A), and decent carrier mobility (∼2.0 cm2/V−1s−1). When a high-k AlOx thin-film is employed as the gate dielectric for the NFs FETs (10 mol% Al–In2O3 NFs), the gate voltage and drain voltage is reduced to 5 V and 3 V, respectively, and the μfe is increased by 6X. Furthermore, 10 mol% Al–In2O3 NFs FETs with enhancement-mode operation were integrated into highly efficient NMOS inverters. All the results indicate that the highly metal-doped In2O3 NFs have practical application for next-generation low-cost, large-area, energy-efficient and high-performance nanoelectronic devices.

Total-Ionizing-Dose Effects in InGaAs MOSFETs With High-k Gate Dielectrics and InP Substrates

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage $V_{\text {th}}$ shifts and subthreshold stretchout ( SS ), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and $I_{d}$ – $V_{\text {gs}}$ measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of $V_{\text {th}}$ and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep.

Optimization of Electrical Properties of MoS2 Field‐Effect Transistors by Dipole Layer Coulombic Interaction With Trap States

The large negative threshold voltage is one of major electrical factors hindering potential applications of MoS2 transistors in low‐power circuit systems. Here, a strategy by forming an electric dipole layer on the surface of MoS2 is presented to optimize the threshold voltage in monolayer polycrystalline MoS2 field‐effect transistors. The electric dipole in an inert non‐conjugated polymer, perfluoropolyether (PFPE), can interact with trapped electrons in the MoS2 active layer and transfer the traps from shallow into deep states, which remarkably improves the threshold voltage. Otherwise, ab initio calculation and molecular dynamics simulation are employed to investigate the transport properties of MoS2 with PFPE. The calculated results imply that localized electrons are dominantly affected by PFPE, while free electrons are irrelevant. This method with dipole layer provides a pathway to implementation of high‐performance MoS2 transistors for future electronic applications.

Modulating Electrical Performances of In2O3 Nanofiber Channel Thin Film Transistors via Sr Doping

AbstractAlthough In2O3 nanofibers (NFs) are considered as one of the fundamental building blocks for future electronics, the further development of these NFs devices is still seriously hindered by the large leakage current, low on/off current ratio (Ion/Ioff), and large negative threshold voltage (VTH) due to the excess carriers existed in the NFs. A simple one‐step electrospinning process is employed here to effectively control the carrier concentration of In2O3 NFs by selectively doping strontium (Sr) element to improve their electrical device performance. The optimal devices (3.6 mol% Sr doping concentration) can yield the high field‐effect mobility (μfe ≈ 3.67 cm2 V−1 s−1), superior Ion/Ioff ratio (≈108), and operation in the energy‐efficient enhancement‐mode. High‐κ Al2O3 thin films can also be employed as the gate dielectric to give the gate voltage greatly reduced by 10× (from 40 to 4 V) and the μfe substantially increased by 4.8× (to 17.2 cm2 V−1 s−1). The electrospun E‐mode Sr‐In2O3 NF field‐effect transistors (NFFETs) can as well be integrated into full swing of inverters with excellent performances, further elucidating the significant advance of this electrospinning technique toward practical applications for future low‐cost, energy‐efficient, large‐scale, and high‐performance electronics.

The effect of interface-induced structural properties of the pentacene accumulation layer on the threshold voltage: Pentacene monolayer transistors

The effect of pentacene/gate dielectric interface-induced structural properties of a pentacene monolayer (ML) close to the SiO2 gate dielectric on the threshold voltage in the field effect transistor (FET) and van der Pauw was addressed using atomic force microscopy and near edge X-ray absorption fine structure spectroscopy (NEXAFS). Our study reveals that large negative threshold voltage found in FET and van der Pauw devices is not closely correlated to the molecular orientation and the grain size of pentacene molecules in direct contact with the SiO2 gate dielectric. In concluding our finding, NEXAFS results in the ultrathin pentacene film within the carrier accumulation thickness regime, characterized by Debye length, were correlated to the magnitude of the threshold voltage from field effect devices. Our work motivates finding and visualizing interface-induced structural properties that are directly correlated to the magnitude of the threshold voltage.

Suppression in the Negative Bias Illumination Instability of ZnSnO Thin-Film Transistors Using Hafnium Doping by Dual-Target Magnetron Cosputtering System

In this paper, the highly improved negative bias illumination stress (NBIS) stability of zinc-tin-oxide (ZTO) thin-film transistors (TFTs) is achieved by Hf doping, using dual-target magnetron cosputtering system. Compared with a large negative threshold voltage shift ( $\vartriangle V_{T})$ of 9 V in pristine ZTO TFT, the Hf-doped ZTO TFTs shows superior stability and device D only shows 1.9 V negative $\vartriangle V_{T}$ under the same NBIS. The enhancement in NBIS stability of Hf-doped ZTO TFTs is attributed to a lower oxygen vacancy concentrations and a fewer interface trap states suppressed by Hf ion. The decrease of oxygen vacancy concentrations and interface trap states are confirmed by X-ray photoelectron spectroscopy measurement and capacitance voltage ( $C$ – $V$ ) measurement, respectively. It is consistent with trap density extracted from temperature-dependent field-effect measurements, which verifies further the factor of the improvement of in NBIS stability of Hf-doped ZTO TFTs.

Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO2 and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO2 gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements.

High performance IGZO/TiO2 thin film transistors using Y2O3 buffer layers on polycarbonate substrate

In this work, we fabricate IGZO TFT devices on flexible substrate at room temperature. The IGZO/TiO2 TFT has small subthreshold swing of 0.16 V/dec, but suffers large gate leakage and negative threshold voltage. However, the TiO2 TFT with Y2O3 buffer layers shows improved characteristics including a low threshold voltage of 0.55 V, a small sub-threshold swing of 0.175 V/decade and high field-effect mobility of 43 cm2/Vs. Such good performance can be attributed to the enhanced capacitance density and lowered gate leakage owing to the integration of large band gap Y2O3 and low-temperature higher-κ TiO2.

Effect of an Upward and Downward Interface Dipole Langmuir–Blodgett Monolayer on Pentacene Organic Field-Effect Transistors: A Comparison Study

We studied carrier behaviors of pentacene organic field-effect transistors (OFETs) with an upward and a downward orientation dipole monolayer, inserted between the organic active layer and gate insulator by the Langmuir–Blodgett technique. The OFETs with an upward orientation of dipole monolayer showed large negative threshold voltage and high contact resistance compared with the reference OFETs without dipole monolayer, while the OFETs with a downward orientation dipole monolayer exhibited positive threshold voltage and low contact resistance. Based on the findings from this comparison study, we argued that using interface dipole monolayer is a useful way to design OFET performance.

Effects of low-temperature ozone annealing on operation characteristics of amorphous In–Ga–Zn–O thin-film transistors

Effects of low-temperature annealing were examined for amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs). In a previous study, we reported that O2 annealing is effective to improve performances of a-IGZO TFTs when annealed at ≥300°C, but causes large negative threshold voltage shift when annealed at ≤ 200°C. Here, we examined effects of ozone (O3) annealing on physical properties and TFT characteristics of a-IGZO in comparison with conventional O2 annealing. We found little differences in chemical composition, band gap and photoemission spectra between the O2 and the O3 annealed films. On the other hand, free electron density was suppressed well by the O3 annealing even at low temperatures ≤200°C. Moreover, even at 150°C, the TFTs characteristics were improved to the subthreshold voltage swing of 217mV/decade, the saturation mobility of ~11.4cm2(Vs)−1 and the threshold voltage of 0.1V by the O3 annealing. It was also found that the effects of the O3 annealing is more effective for thicker channel TFTs, which would be due to stronger oxidation power and the larger diffusion constant of oxygen atoms produced from O3 molecules than those of O2. These results substantiate that the O3 annealing is more effective to improve TFT characteristics in particular for low-temperature processes at ≤200°C.

Anomalous Threshold Voltage Shift and Surface Passivation of Transparent Indium–Zinc–Oxide Electric-Double-Layer TFTs

Threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability and surface passivation effect of transparent indium-zinc-oxide electric-double-layer thin-film transistors (TFTs) are investigated. Unpassivated devices show a large negative threshold voltage shift of 0.68 V in the beginning of light-illuminated negative gate bias stress. Under longer time stress, anomalous positive <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts are observed for both unpassivated and passivated TFTs, which is due to the mobile ions drifting in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based solid-electrolyte gate dielectric. After surface passivation, the devices show neglectable negative <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts of less than 0.1 V due to the protection of channel against the photodesorption of adsorbed oxygen ions.

Function of Interfacial Dipole Monolayer in Organic Field Effect Transistors

The effect of interfacial dipole monolayer on carrier injection property of pentacene OFET was studied to understand the origin of contact resistance, which was evaluated from a modified transmission line model. The results showed the contact resistance of pentacene OFET with the dipole monolayer is much higher. This large discrepancy was found due to a small potential drop difference at the interface generated by the dipole monolayer. In addition, the strong local electric field confirmed the reason for the large negative threshold voltage shift. These studies show the importance of local electric field at pentacene–SiO2 interface generated by the dipole monolayer.

Modeling of threshold voltage in pentacene organic field-effect transistors

To understand the physical meaning of threshold voltage in organic field-effect transistors (OFETs), we studied the threshold voltage (shift) dependence on gate-insulator thickness as well as active-layer thickness, by using pentacene OFETs with and without a dipole interlayer between pentacene active layer and SiO2 gate insulator. Results showed that the presence of dipole monolayer caused a large threshold voltage shift and there was a linear relationship between the threshold voltage shift and the layer thickness of pentacene as well as SiO2. Assuming the pentacene film is a dielectric layer and the threshold voltage in pentacene OFET is determined from a zero-electric-field condition at the gate insulator interface, we propose a model based on compensation of the local electric field in the vicinity of semiconductor and gate insulator interface. The model well accounts for both the large negative threshold voltage shift and the linear relation. These findings reveal the importance of interfacial electric field for analyzing organic devices.

Tuning of Threshold Voltage in Organic Field-Effect Transistor by Dipole Monolayer

We have studied the threshold voltage shift of top-contact organic field-effect transistors (OFETs) with a dipole monolayer between pentacene active layer and SiO2 gate insulator. Since dipole moment projection in normal of the monolayer can be regulated by changing the ordering, the relationship between threshold voltage shift and spontaneous polarization of the monolayer has been gained. Experimental results show the dipole monolayer causes a large negative threshold voltage shift and the shift is linearly proportional to the polarization of the monolayer. We propose a dipole layer model to interpret the observed phenomena with an assumption that the threshold voltage shift is due to compensation of electric field in organic semiconductor layer induced by the dipole monolayer, which is uncommon for the general consideration. Excitingly, a good agreement between the experiment and the analysis shows validity of our modeling and provides the capability of tuning threshold voltage for OFET devices.

Device characteristics improvement of a-In–Ga–Zn–O TFTs by low-temperature annealing

A low-temperature process to improve performances of a-In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) fabricated at room temperature was examined. Two deposition methods, pulsed laser deposition (PLD) and RF magnetron sputtering were employed to deposit the a-IGZO channels. For the PLD case, the TFT characteristics were improved significantly by wet annealing at dew point (d.p.) of 50 °C at the annealing temperature of 200 °C. For the sputtered TFTs, a wider range of annealing temperature from 100 to 200 °C was examined. It was found that annealing at ≥ 150 °C improved the TFT characteristics when dry annealing was employed. On the other hand, wet annealing also improved μ sat and S values, but very large negative threshold voltage ( V th) shift was observed. These results indicate that the annealing at 150 °C is enough to obtain mobility ( μ sat) as large as 8 cm 2 Vs − 1 , but annealing temperature as high as 200 °C provides larger μ sat comparable to those obtained by 400 °C annealing. It is speculated that the large negative V th shift originates from compensated donors in as-deposited sputtered films.

Recent advances and current challenges in the search for high mobility band-edge high-k/metal gate stacks

Continued miniaturization of the different physical elements of a Si MOSFET required in order to attain higher transistor performance and greater economies of scale have spurred the need for significant materials innovations. This is most apparent in the search for the ideal high-k/Metal Gate stack that would replace conventional SiON/Poly-Si gate stacks. In this paper, we will review some of the recent advances and remaining challenges for high-k/Metal Gate stacks. It is shown that significant progress has been made towards improving electron mobility in HfO 2/Metal Gate stacks by a combination of high temperature processes, nitrogen free interfaces and optimized metal deposition processes which result in mobility values competitive with SiON/Poly-Si. In addition by inserting nanoscale layers that comprise strongly electropositive gp. IIA and IIIB elements in between the HfO 2and metal electrode stack have resulted in high mobility, band-edge aggressively scaled High-k/Metal Gate stacks. While much progress has been made with nMOSFET stacks, it will also be shown that a number of roadblocks remain with obtaining a similar solution for pMOSFET stacks, primarily due to the presence of thermally activated oxygen vacancies that induce large negative threshold voltage shifts towards midgap in HfO 2/high workfunction metal stacks.

Radiation-induced off-state leakage current in commercial power MOSFETs

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO/sub 2/) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.