Large Input Capacitance Research Articles

Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, performance at 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> and 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery.

Design and optimization of the CSA-based readout electronics for STCF ECAL

In this paper, a front-end electronics system based on charge sensitive amplifier (CSA) is designed to read out the signal of pure CsI (pCsI) crystal, which is the basic option of Super Tau-Charm Facility (STCF) electromagnetic calorimeter (ECAL). By noise analysis and on-board testing, parameters of the readout circuit are optimized. Thus the noise of the system with large input capacitance of avalanche photodiode (APD) is significantly reduced. A noise level of 675 electrons for electronics alone and 1025 electrons with S8664-0505 APD is realized, which satisfies the project requirements.

Impedance-Oriented Transient Instability Modeling of SiC mosfet Intruded by Measurement Probes

Due to the breakneck switching speed, SiC mosfet is extremely sensitive to parasitics in the power device, circuit layout, and also measurement probe. It is not clear how the parasitics of measurement probes affect the transient stability of SiC mosfet , and it poses an unsolved challenge for the industrial field. This paper focuses to uncover the transient instability mechanism of SiC mosfet intruded by probes. Mathematical and circuit models of voltage and current probes are created, by considering the parasitics, input impedance, and bandwidth issues. To reveal the stability principles of SiC mosfet associated with probes, impedance-oriented and heterogeneity-synthesized models combining device with probes are proposed. Furthermore, an assessment methodology and root locus analysis are presented to demonstrate the transient stability schemes and the stable boundaries of SiC mosfet influenced by multiple factors, including probe parasitics, device parameters, gate resistances, and snubber circuits. Comparative experiments are presented to confirm the transient behaviors of SiC mosfet intruded by probe parasitics and regulated by control circuits. It is proven that, because of low bandwidth specifications, the large input capacitance of the voltage probe and coil inductance of the current probe degrade the transient stability of SiC mosfet . Due to the deteriorated stability margin of SiC mosfet intruded by the inserted parasitics of probes, instability may also be activated by using the small gate resistance. The snubber circuit is helpful to enhance the transient stability. Advanced probes with high bandwidth and high impedance are crucially needed for stable measurement of wide bandgap power devices like SiC mosfet .

A Simple SR Gate Driving Circuit With Reduced Gate Driving Loss for Phase-Shifted Full-Bridge Converter

The phase-shifted full-bridge (PSFB) converter with synchronous rectifier (SR) is one of the most attractive dc–dc converters for the server power supply due to its high power capability and small secondary ripple current with the output inductor. Moreover, it can more reduce the secondary conduction loss by using parallel-connected mosfet s in SR. However, due to large input capacitance of the parallel-connected mosfet s in SR, the PSFB converter has large SR gate driving loss, which particularly degrades the light load efficiency. Thus, in this paper, one additional resistor is added to the conventional SR gate driving circuit to recycle the gate driving energy. As a result, the proposed circuit can improve the light load efficiency of the PSFB converter without operation mode change, additional controls, and complex circuits. The most advantage of the proposed circuit is that it is very simple and available to any other SR gate driver IC. The validity of the proposed circuit is confirmed by experimental results from a prototype with 340–400 V input and 12 V/66.66 A output.

A cascode linear power amplifier with reduced capacitance variation of common gate transistors

ABSTRACT:A common‐gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

ELine10k: A High Dynamic Range Front-End ASIC for LCLS Detectors

eLine10k is a fast-frame, 64-channel readout ASIC for SLAC Linac Coherent Light Source (LCLS) detectors. The circuit has been designed to integrate the charge from high-capacitance 2D sensors with rolling shutter and 1D strip sensors. It is suitable for applications requiring large input signal range, on the order of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$10^{4}$</tex> </formula> photons/pixel/pulse at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$8~\hbox{keV} (22~\hbox{Me}^{-})$</tex></formula> , and a resolution of half a photon FWHM ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$500~\hbox{e}^{-}\ \hbox{r.m.s.}$</tex> </formula> ). 2D sensors with a rolling shutter like the X-ray Active Matrix Pixel Sensor (XAMPS), for which the ASIC has been optimized, present large input capacitance to each channel leading to stringent noise optimization requirements. The large required number of pixels per channel, and the fixed LCLS beam period impose limitations on the time available for the readout of each single pixel. Giving the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system, providing low-noise charge integration, filtering and correlated double-sampling, and a processing speed up to 500 k pixel/s on each channel. To cope with the large input dynamic range, a charge pump scheme has been implemented providing on-chip 4-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into an analog memory, multiplexed and measured with the required resolution using an external ADC. In this paper, the ASIC architecture and performance of the final release are presented.

Performance of RPCs and diamond detectors using a new very fast low noise preamplifier

The new high energy high luminosity experiments require an improvement in both the counting rate and the space resolution for the detectors. This improvement can be achieved by reducing the charge per count, however this implies a need for a better signal to noise ratio in the signal processing. In this article we will show the performances of diamond detectors and RPCs using a new preamplifier with low noise (500–1000 electrons RMS), fast shaping (about 10 ns) and large input capacitance.

Wide-band current preamplifier for conductance measurements with large input capacitance

A wide-band current preamplifier based on a composite operational amplifier is proposed. It has been shown that the bandwidth of the preamplifier can be significantly increased by enhancing the effective open-loop gain. The described 10(7) V/A current gain preamplifier had the bandwidth of about 100 kHz with the 1 nF input shunt capacitance. The measured preamplifier current noise was 46 fA/√Hz at 1 kHz, close to the design noise minimum. The voltage noise was found to be about 2.9 nV/√Hz at 1 kHz, which is in a good agreement with the value expected for the particular operational amplifier used in the input stage. By analysing the total produced noise we found that the optimal frequency range suitable for the fast lock-in measurements is from 1 kHz to 2 kHz. To obtain the same signal-to-noise ratio, the reported preamplifier requires ~10% of the integration time needed in measurements made with a conventional preamplifier.

High performance power-configurable preamplifier in a high-density parallel optical receiver

A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate (FCG) stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom consuming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute inductors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature (PVT) variation. Two representative samples provide a trans-impedance gain of 53.9 dBΩ, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBΩ, a 3-dB bandwidth of 8.1 GHz, a power dissipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than . The chip area is only 0.08 × 0.08 mm2.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain-machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode-neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal-oxide-semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 μA, modulating input referred noise from 9.92 μV to 3.9 μV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

A low-noise, low stored energy preamplifier for high-voltage radiation detectors

A low-noise preamplifier with very low stored energy has been developed for use with high-voltage radiation detectors. The input will withstand 3.5 kV, has a physical capacitance to ground of 200 pF, and an effective “small signal” capacitance of ∼30 nF. When connected to a high-voltage electrode, the low physical input capacitance to ground limits the stored energy and helps protect the detector system should an accidental discharge occur. The large effective input capacitance minimizes the voltage transient on the high-voltage electrode that occurs during charge collection, thus lowering the charge that is capacitively coupled to surrounding electrodes from this transient. If the surrounding electrodes are part of a position sensing readout, then this coupled charge is distributed uniformly among readout electrodes and is added to the signal charge induced by the motion of charge carriers containing position information. This introduces an error into the position centroid calculation. The preamplifier presented here greatly reduces this effect while keeping stored energy low. Equivalent input noise charge (ENC) is 256 electrons RMS when using a 250 ns unipolar shaping amplifier and no input capacitance. With input capacitances of 18 and 223 pF, the noise increases to 361 and 1766 electrons RMS, respectively.

Anode front-end electronics for the cathode strip chambers of the CMS Endcap Muon detector

The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183,000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier–shaper–discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3×2.5 m 2) and for the large input capacitance (up to 200 pF). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2–3 ns). The delay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This paper presents the anode front-end electronics structure and results of the preproduction and the mass production tests, including radiation resistance and reliability tests. The special set of test equipment, techniques, and corresponding software developed and used in the test procedures are also described.

Delta: a charge sensitive front-end amplifier with switched gain for low-noise, large dynamic range silicon detector readout

The design and results of a radiation hard switched gain charge amplifier optimised for a large dynamic range and large input capacitance are described. The peaking time is 25 ns , dynamic ranges are 0.1–50 minimum ionising particles (MIPs) (high gain) and 1–400 MIPs (low gain), signal to noise ( S/ N)>10 for C in <56 pF and radiation tolerance to 10 Mrads(Si) and 4×10 13 n cm −2 .

A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC

The design of a multibit /spl Delta//spl Sigma/ converter is presented. It uses a third-order 4-bit /spl Delta//spl Sigma/ topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz. Behavioral models are used to determine several building block specifications. An accurate model is used to analyze the combined effect of the dominant closed loop pole of the operational transconductance amplifier (OTA), the slew rate and the nonzero switch resistance. It is shown that the offset requirements for the quantizer result in a large input capacitance of the quantizer. Therefore scaling of the OTAs, as classically employed in single-bit /spl Delta//spl Sigma/ converters, can no longer be used. For an oversampling ratio of only 24, the converter achieves a signal-to-noise ratio of 95 dB, a signal-to-noise-plus-distortion ratio of 89 dB and an input dynamic range of 97 dB after comb-filtering. The converter is sampled at 60 MHz, resulting in a 2.5 MS/s output rate. It is implemented in a standard 0.65-/spl mu/m CMOS technology, occupies 5.3 mm/sup 2/ and consumes 295 mW from a 5-V power supply. When clocked at 100 MHz with an oversampling ratio of 8, a 12-bit resolution is achieved at an output rate of 12.5 MS/s.

A new large area monolithic silicon telescope

A new prototype of large area (20×20 mm 2) monolithic silicon telescope with an ultrathin Δ E stage (1 μm) has been built and tested. A particular mask for the ground electrode has been developed to improve the charge collection reducing the induction between the E and Δ E stages. A special designed preamplifier has been used for the readout of the signal from the Δ E stage to overcome the problem of the large input capacitance (40 nF). A rather low energy threshold charge discrimination has been obtained. Small side effects due to the electric field deformation near the ground electrode were observed and quantified.

Radiation damage investigation for the design of a hardened fast bipolar monolithic charge sensitive preamplifier

In order to implement a high-speed, radiation hardened, Charge Sensitive Preamplifier (CSP) in the monolithic 2 μ m BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Furthermore, also monolithic CSPs, realized with the same technology, were irradiated and investigated. Results on the neutron irradiation effect on the base spreading resistance ( r bb′ ) of the CSP input NPN-transistor are presented. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. Results confirm that the HF2CMOS process is suitable to sustain the radiation environment of the future LHC collider. A design for a new CSP version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time.

Radiation damage investigation for the design of a hardened fast bipolar monolithic charge sensitive preamplifier

In order to implement a high-speed, radiation hardened, charge sensitive preamplifier (CSP) in the monolithic 2 μm BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Furthermore, also monolithic CSPs, realized with the same technology, were irradiated and investigated. Results on the neutron irradiation effect on the base spreading resistance ( r bb′) of the CSP input NPN-transistor are presented. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. Results confirm that the HF2CMOS process is suitable to sustain the radiation environment of the future LHC collider. A design for a new CSP version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time.

Nanosecond switching using power MOSFETs

It is shown that using the secondary breakdown effect of a bipolar transistor, often called an avalanche transistor, the large input capacitance of a power MOSFET may be charged very quickly. A power MOSFET driven by an avalanche transistor is used to generate electrical pulses of &amp;gt;800 V into 50 Ω with rise times of approximately 3 ns. The output pulse amplitude can be varied by adjusting the drain-source voltage of the power MOSFET. The trigger delay of this circuit is approximately 5 ns, with jitter of &amp;lt;100 ps. This circuit has been used to generate pulses at a repetition rate of greater than 1 kHz.

The maximal area of superconducting tunneling junction x-ray detectors determined by the required signal-to-noise ratio

Abstract The intrinsically high energy resolution of superconducting tunneling junctions (STJ) requires a low noise charge sensitive amplifier circuit. The noise sources of such a junction + amplifier circuit are discussed. The dominant noise sources are the series noise and the 1 f flicker noise of the FET input stage, amplified by the large input capacitance of the STJ-detector. Means to reduce this capacitance are discussed. Reducing the preamplifier noise by a factor of two and the height of the potential barrier of the insulating layer by two orders of magnitude, by keeping the large conductance of the junction constant, would allow an increase in junction area by a factor of 15.