Abstract
In order to implement a high-speed, radiation hardened, Charge Sensitive Preamplifier (CSP) in the monolithic 2 μ m BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Furthermore, also monolithic CSPs, realized with the same technology, were irradiated and investigated. Results on the neutron irradiation effect on the base spreading resistance ( r bb′ ) of the CSP input NPN-transistor are presented. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. Results confirm that the HF2CMOS process is suitable to sustain the radiation environment of the future LHC collider. A design for a new CSP version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time.
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