Large Gate Width Research Articles

C‐band 180‐nm CMOS transmitter front‐end with a three‐stage power amplifier for phased array applications

AbstractA fully differential transmitter front‐end with multistage power amplifiers and a 7‐bit phase shifter were implemented in a 180‐nm CMOS process. RC feedback and cross‐coupling circuits were adopted to improve the stability of the power amplifiers. For the final power stage, a four‐transistor in‐parallel architecture was used to obtain a large total gate width, while maintaining a compact size with relatively small parasitic effects. The measured saturated output power (Psat) of the fabricated transmitter chip is 21.3−22 dBm, with a system efficiency of 24%−28.2% at 5−7 GHz, and the root‐mean‐square phase and gain error are below 1.40° and 0.28 dB, respectively, with 7‐bit phase resolution.

NIR Fluorescence lifetime macroscopic imaging with a time-gated SPAD camera.

The performance of SwissSPAD2 (SS2), a large scale, widefield time-gated CMOS SPAD imager developed for fluorescence lifetime imaging, has recently been described in the context of visible range and fluorescence lifetime imaging microscopy (FLIM) of dyes with lifetimes in the 2.5 - 4 ns range. Here, we explore its capabilities in the NIR regime relevant for small animal imaging, where its sensitivity is lower and typical NIR fluorescent dye lifetimes are much shorter (1 ns or less). We carry out this study in a simple macroscopic imaging setup based on a compact NIR picosecond pulsed laser, an engineered diffuser-based illumination optics, and NIR optimized imaging lens suitable for well-plate or small animal imaging. Because laser repetition rates can vary between models, but the synchronization signal frequency accepted by SS2 is fixed to 20 MHz, we first checked that a simple frequency-division scheme enables data recording for different laser repetition rates. Next, we acquired data using different time gate widths, including gates with duration longer than the laser period, and analyzed the resulting data using both standard nonlinear least-square fit (NLSF) and phasor analysis. We show that the fixed synchronization rate and large gate widths characterizing SS2 (10 ns and over) are not an obstacle to accurately extracting lifetime in the 1 ns range and to distinguishing between close lifetimes. In summary, SS2 and similar very large gated SPAD imagers appear as a versatile alternative to other widefield time-resolved detectors for NIR fluorescence lifetime imaging, including preclinical molecular applications.

Lateral GaN Jfet Devices on Large Area Engineered Substrates for Robust Power Switching

GaN-based power switching devices are of significant interest for high efficiency power conversion circuits in medium voltage applications. However, there are still significant challenges preventing mass production and widespread adoption. In particular, lateral HEMT devices lack avalanche capability for rugged power switching, vertical device technology is not mature, the manufacturing cost associated with small diameter substrates is relatively high, and CTE mismatch issues create limitations on epi thickness as well as bow issues for GaN-on-Si. As a scalable substrate solution, Qromis, Inc. has developed commercial substrates designated QST™ which are engineered to be thermally matched to GaN, enabling thick epitaxial layers capable of >1kV devices on 200 mm diameter wafers suitable for fabrication in a CMOS fabrication facility. Taking advantage of this platform, we present a GaN-based lateral junction gate field effect transistor (JFET) device structure for robust power switching. The p-GaN gate functions to collect secondary holes while a second buried p-GaN blocking layer is implemented to pull the electric field below the surface as in a Reduced Surface Field (RESURF) structure. Unlike a HEMT process, the LJFET epi design and process sequence requires appropriate design of the doping in the buffer, gate, and channel layers for charge balancing, and additional process modules for N+ doping for source/drain contact (via ion implantation), low-damage p+ etching to define the gate, and N implantation to partially compensate the p- layer for field management. These steps have been independently optimized. Device testing indicated high current capability (>1A) in large gate width devices and high current density (~200 mA/mm) in smaller devices. The discrepancy is attributed to a processing issue creating spreading resistance in the ohmic contacts indicating a need for thick metallization. Gate continuity was tested by electroluminescence from the forward biased p-n junction, and breakdown tests indicated >1kV blocking capability with low leakage current. In summary, a conceptual prototype for a lateral GaN JFET device was demonstrated experimentally with promising current density and breakdown performance.

Lateral GaN JFET Devices on Large Area Engineered Substrates

Lateral GaN-based p-n junction gated field effect transistor (LJFET) power transistors on large area substrates were fabricated as a proof-of-concept to evaluate candidate power switching devices that could be designed with avalanche breakdown capability. The devices performed to design specifications aimed at demonstrating a device suitable for operation in cascode with a normally-off low-voltage Si based transistor companion. The maximum current density was 200 mA/mm and threshold voltage was −30V. Large gate width devices (40mm) exhibited >1A current. The devices have blocking capability to 800V. Initial testing of the switching dynamics indicates low dynamic RON even with an un-optimized buffer.

Direct Current Characteristics of AlGaN/GaN High-Electron-Mobility Transistors with Different Channel Widths

AlGaN/GaN high-electron-mobility transistors with different channel configurations were fabricated and characterized. Channel configuration was designed to have the source, gate, and drain metal contacts of the same size but with different channel widths, which was achieved by the current blocking region. Current density, subthreshold swing, and transconductance (gm) improved with the decreasing channel width. A significant improvement was observed in gm because of a large gate width (WG) to channel width (Wchannel) ratio. A device with a WG/Wchannel of 4 has a gm of 239 mS/mm, whereas a device with a WG/Wchannel of 1 has a gm of 127 mS/mm.

Time-resolved evaluation of uranium plasma in different atmospheres by laser-induced breakdown spectroscopy

This work reports spectroscopic studies of uranium containing plasma generated in air and argon environments. The 532 nm Q-switched Nd:YAG laser generates the optical breakdown plasma, which was recorded by a spectrometer and an intensified charge coupled device having a resolution of 25 pm. Neutral and ionized uranium lines in the wavelength range of 385.8–391.9 nm indicate significant width and shift variations during the first few microseconds. Electron temperature and density of the plasma are determined using the Boltzmann plot and the Saha–Boltzmann equation at various time delay. The study reveals the power law decay pattern of electron temperature and density, which changes to exponential decay pattern if large gate-width is used to acquire the signal, due to an averaging effect.

Improved Linearity with Polarization Coulomb Field Scattering in AlGaN/GaN Heterostructure Field-Effect Transistors

The single-tone power of the AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths was measured. A distinct improvement in device linearity was observed in the sample with a larger gate width. The analysis of the variation of the parasitic source access resistance showed that, as the gate bias is increased, the polarization Coulomb field scattering can offset the increased polar optical phonon scattering and improve the device linearity. This approach is shown to be effective in improving the device linearity of AlGaN/GaN HFETs.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

Stability Investigation of Large Gate-Width Metamorphic High Electron-Mobility Transistors at Cryogenic Temperature

An investigation of metamorphic high electron mobility transistor stability at cryogenic temperature is presented in this paper. Unlike in the case of two-finger transistors, the measurements of cooled four-finger devices with large gate widths exhibit unstable behavior in the form of steps in the current–voltage characteristics, discontinuities in the transconductance, and reduced gain. This unstable behavior has hampered the reliable realization of low-noise amplifiers for cryogenic applications. We study different gate-width devices with a multiport transistor model, allowing the separation of gate and drain feeder structures from the active part of the transistor. The simulation reveals the presence of resonances in the frequency region of several hundreds of gigahertz. We demonstrate that the resonances disappear when an air bridge is placed across the fingers of the drain feeder structure, and confirm the stabilizing effect of the air bridge both on device and circuit level by cryogenic measurements.

Secondary plasma formation after single pulse laser ablation underwater and its advantages for laser induced breakdown spectroscopy (LIBS).

In this work we present studies of spatial and temporal plasma evolution after single pulse ablation of an aluminium target in water. The laser ablation was performed using 20 ns long pulses emitted at 1064 nm. The plasma characterization was performed by fast photography, the Schlieren technique, shadowgraphy and optical emission spectroscopy. The experimental results indicate the existence of two distinct plasma stages: the first stage has a duration of approximately 500 ns from the laser pulse, and is followed by a new plasma growth starting from the crater center. The secondary plasma slowly evolves inside the growing vapor bubble, and its optical emission lasts over several tens of microseconds. Later, the hot glowing particles, trapped inside the vapor cavity, were detected during the whole cycle of the bubble, where the first collapse occurs after 475 μs from the laser pulse. Differences in the plasma properties during the two evolution phases are discussed, with an accent on the optical emission since its detection is of primary importance for LIBS. Here we demonstrate that the LIBS signal quality in single pulse excitation underwater can be greatly enhanced by detecting only the secondary plasma emission, and also by applying long acquisition gates (in the order of 10-100 μs). The presented results are of great importance for LIBS measurements inside a liquid environment, since they prove that a good analytical signal can be obtained by using nanosecond pulses from a single commercial laser source and by employing cost effective, not gated detectors.

High speed multispectral fluorescence lifetime imaging

We report a spectrally resolved fluorescence lifetime imaging system based on time gated single photon detection with a fixed gate width of 200 ps and 7 spectral channels. Time gated systems can operate at high count rates but usually have large gate widths and sample only part of the fluorescence decay curve. In the system presented in this work, the fluorescence signal is sampled using a high speed transceiver. An error analysis is carried out to characterize the performance of both lifetime and spectral detection. The effect of gate width and spectral channel width on the accuracy of estimated lifetimes and spectral widths is described. The performance of the whole instrument is evaluated at count rates of up to 12 MHz. Accurate fluorescence lifetimes (error < 2%) are recorded at count rates as high as 5 MHz. This is limited by the PMT performance, not by the electronics. Analysis of the large spectral lifetime image sets is challenging and time-consuming. Here, we demonstrate the use of lifetime and spectral phasors for analyzing images of fibroblast cells with 2 different labeled components. The phasor approach provides a fast and intuitive way of analyzing the results of spectrally resolved fluorescence lifetime imaging experiments.

Advanced CAD tool for noise modeling of RF/microwave field effect transistors with large gate widths

In the millimeter-wave frequency range, electromagnetic (EM) effects can significantly influence a device behavior. As the core of modern communication systems, active devices such as field effect transistors (FETs) require up-to-date models to accurately integrate such effects, especially in terms of noise performance since most of communication systems operate in noisy environments. Furthermore, to keep low-noise amplification over a wide frequency band, the transistor noise resistance Rn must be substantially reduced to make the system insensitive to impedance matching. Since this can be realized through large gate-width devices, a novel large gate-width FET noise model is proposed which efficiently integrates EM wave propagation effects, one of the most important EM effects in mm-wave frequencies.

AlGaN/GaN epitaxy and technology

We present an overview on epitaxial growth, processing technology, device performance, and reliability of our GaN high electron mobility transistors (HEMTs) manufactured on 3- and 4-in. SiC substrates. Epitaxy and processing are optimized for both performance and reliability. We use three different gate lengths, namely 500 nm for 1–6 GHz applications, 250 nm for devices between 6 and 18 GHz, and 150 nm for higher frequencies. The developed HEMTs demonstrate excellent high-voltage stability, high power performance, and large DC to RF conversion efficiencies for all gate lengths. On large gate width devices for base station applications, an output power beyond 125 W is achieved with a power added efficiency around 60% and a linear gain around 16 dB. Reliability is tested both under DC and RF conditions with supply voltage of 50 and 30 V for 500 and 250 nm gates, respectively. DC tests on HEMT devices return a drain current change of just about 10% under IDQ conditions. Under RF stress the observed change in output power density is below 0.2 dB after more than 1000 h for both gate length technologies.

Uniformly Distributed Wideband Metal–Oxide–Semiconductor Field-Effect Transistor Model for Complementary Metal–Oxide–Semiconductor Radio-Frequency Integrated Cirsuits Applications

In this paper, a uniformly distributed wide-band metal–oxide–semiconductor field-effect transistor (MOSFET) model constructed by several same unit cells in parallel is presented. The kink phenomenon of scattering parameter S11 due to the distributed gate-resistance of MOSFETs can be fitted well by this model. Good agreement between the measured and modeled results of scattering parameters S22, current gain H21, and unilateral gain U are also demonstrated. In addition, the impact of distributed gate-resistance on cut-off frequency ( fT) and maximum oscillation frequency ( fmax) performances of single gate-finger MOSFETs with large gate-width of 20, 40, 80, 120, and 160 µm are quantitatively characterized and analyzed.

TLP Characterization of large gate width devices

The maximum transient voltage of a MOSFET device is one of the key parameters for power applications. Therefore, transmission line pulse (TLP) characterization is used to assess this. TLP measurements on large gate width devices are difficult to perform due to gate oscillations. In this paper, a method to avoid oscillation when measuring large gate width devices is presented. Device simulations are presented showing gate side oscillation triggered by the rising edge of the 100 ns TLP pulse. Adding a resistor in series with the gate largely damps the oscillation. Comparison between system level simulation and captured TLP waveforms is done and the correlation is discussed.

Analysis of RF scattering parameters and noise and power performances of RF‐power MOS in 0.15‐μm RF cmos technology for RF SOC applications

AbstractIn this paper, we demonstrate an analysis of the effects of transconductance gm on the kink phenomenon of the scattering parameters S11, S22, S21, and S12 of RF power n‐MOSFETs in 0.15‐μm RF CMOS technology for RF SOC applications. It is found that either the increase of the device's width or the increase of the gate‐source voltage VGS (when its corresponding gm is smaller than the maximum gm) and the decrease of the measurement temperature can enhance the kink effect of both S11 and S22 due to the increase of gm. The anomalous dip in the S11 and S22 of RF power n‐MOSFETs can also be interpreted in terms of poles and zeros. In addition, we conclude that a device with larger gate width or larger gm exhibits better RF noise and power performances because of higher gain (or gm) and the lighter effect of the parasitic extrinsic elements. The present analyses enable RF engineers to understand more deeply the behaviors of S parameters, RF noise and power performances of RF power MOSFETs, and hence is helpful for them to create a fully scalable wideband RF‐power MOS or CMOS model for RF SOC applications. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 41: 191–196, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20089

Monte Carlo particle-based simulations of deep-submicron n-MOSFETs with real-space treatment of electron–electron and electron–impurity interactions

In modern deep-submicron devices, for achieving optimum device performance, the doping densities must be quite high. This necessitates a careful treatment of the short- and long-range electron–electron and electron–impurity interactions. We have shown before that by using a corrected Coulomb force, in conjunction with a proper cutoff range, one can properly account for the short-range portion of the force. Our approach naturally incorporates multi-ion contributions, local distortions in the scattering potential due to the movement of the free charges, and carrier-density fluctuations. The doping dependence of the low-field electron mobility obtained from 3D resistor simulations closely followed the experimental results, thus proving the correctness of our approach. Here, we discuss how discrete impurity effects affect the threshold voltage of ultra-small n-channel MOSFETs with gate lengths ranging from 50 to 100 nm. We find that the fluctuations in the threshold voltage increase with increasing the oxide thickness and substrate doping. The averaging effect over the width of the device leads to significantly smaller fluctuations in the threshold voltage for devices with larger gate width. The observed trends are in agreement with the experimental findings.

Double-doped In/sub 0.35/Al/sub 0.65/As/In/sub 0.35/Ga/sub 0.65/As power heterojunction FET on GaAs substrate with 1 W output power

A double-doped metamorphic In/sub 0.35/Al/sub 0.65/As/In/sub 0.35/Ga/sub 0.65/As power heterojunction FET (HJFET) on GaAs substrate is demonstrated. The HJFET exhibits good dc characteristics, with gate forward turn on voltage of 1.0 V, breakdown voltage of 20 V, and maximum drain current of 490 mA/mm. Under RF operation at a frequency of 950 MHz, a power added efficiency of 63% with associated output power of 31.7 dBm is obtained at a gate width of 12.8 mm. This large gate width and state-of-the-art power performance in metamorphic HJFETS were enabled by a selective etching, sputtered WSi gate process and low surface roughness due to an Al/sub 0.60/Ga/sub 0.40/As/sub 0.69/Sb/sub 0.31/ strain relief buffer.

A Study on the Fabrication of a Multigate/Multichannel Polysilicon Thin Film Transistor

In this study, the new polysilicon thin film transistors (TFTs) incorporating a multigate and a multichannel were fabricated and their electrical characteristics were estimated. An average field-effect mobility as high as 30 cm2/Vs was achieved for multigate/multichannel polysilicon TFTs. A subthreshold slope of 3 V/dec and a threshold voltage of 3 V were obtained. The switching ratio was about 105. Through the experimental results, it was found that multigate/multichannel TFTs can overcome the limitation of the multigate TFT whose on-current is smaller than that of a single-gate TFT with the same aspect ratio. Moreover, the bias-dependence of their off-current was not apparent even when the multichannel structure was employed. This is thought to be caused by the increase of the total channel resistance by the division of the channel. Compared with that of the conventional TFT employing the large gate width, the off-current flow in the new multigate/multichannel polysilicon TFT was greatly reduced without much loss of the on-current, in spite of the small total gate width.

A low-noise gate structure for DMOS monolithic devices

The effect of gate topology on the device noise figure of silicon double-diffused metal oxide semiconductor (DMOS) field-effect transistors is demonstrated and gate structures for DMOS devices with a noise figure approaching 1 dB at 500 MHz are presented. An analytical model for the output noise power and noise figure is given. The model is based on the assumptions that the device channel noise power spectrum is not correlated to the gate resistive noise and that the frequency is low enough so that the distributed effects of the gate structure are not significant. From this model, it is predicted that a large gate width is necessary for optimum low-noise performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>