Large Density Of Interface States Research Articles

Graphene transfer passivates GaAs

Graphene–semiconductor junction interface states influence the carrier recombination processes in emerging optoelectronic devices. The large density of interface states in the graphene–GaAs junction is partly formed by oxidation in air of the GaAs surface. A graphene transfer presented herein reduces the arsenic species in the GaAs oxide and maintains the reduction over a span of at least one year. The photoluminescence and terahertz emission spectra show reduced surface trapping of photogenerated carriers in GaAs with graphene-capped oxide. These findings demonstrate a 2D material transfer that passivates a 3D semiconductor surface. A consequence of the passivation is observed by photoreflectance modulation spectroscopy of graphene covered semi-insulating GaAs. The built-in surface field is sufficiently screened by optically pumped carriers to reveal an enhanced excitonic absorption just below the GaAs bandgap. The absorption critical point anomalously red shifts by 4–6 meV from the bulk exciton characteristic energy, an effect we attribute to the exciton absorption occurring closer to the graphene–GaAs interface and influenced by the near-surface GaAs dielectric polarization.

Modeling of carrier scattering in MOS inversion layers with large density of interface states and simulation of electron Hall mobility in 4H-SiC MOSFETs

We formulate scattering mechanisms in quasi-two-dimensional systems with a large density of interface states such as 4H-SiC MOS interfaces, and calculate the electron Hall mobility in 4H-SiC MOS inversion layers by Monte Carlo simulation. In addition to phonon, ionized impurity, and surface roughness scattering, we take account of Coulomb scattering by the electrons trapped at the interface states and the interface fixed charges and scattering by electrically neutral defects. Considering that the number of trapped electrons can be comparable to or larger than that of mobile electrons, the trapped electrons are assumed to contribute to screening as well as scattering. Using the developed model, we analyze the dependence of Hall mobility in 4H-SiC MOS inversion layers on the body acceptor density, temperature, and interface state density. Our calculation reasonably reproduces the experimental behaviors of Hall mobility. We also discuss the physical mechanisms underlying the obtained results.

Electric-field-controlled interface dipole modulation for Si-based memory devices

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO2/Si MOS capacitor where the interface monolayer (ML) TiO2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (Dit). Consequently, we propose, a multi-stacked amorphous HfO2/1-ML TiO2/SiO2 IDM structure to realize a low Dit and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Multi-scale investigation of interface properties, stacking order and decoupling of few layer graphene on C-face 4H-SiC

In this work, we report a multi-scale investigation using several nano-, micro and macro-scale techniques of few layer graphene (FLG) sample consisting of large monolayer (ML) and bilayer (BL) areas grown on C-face 4H-SiC (000-1) by high-temperature sublimation. Single 1 × 1 diffraction patterns are observed by micro-low-energy electron diffraction for ML, BL and trilayer graphene with no indication of out-of-plane rotational disorder. A SiOx layer is identified between graphene and SiC by X-ray photoelectron emission spectroscopy and reflectance measurements. The chemical composition of the interface layer changes towards SiO2 and its thickness increases with aging in normal ambient conditions. The formation mechanism of the interface layer is discussed. It is shown by torsion resonance conductive atomic force microscopy that the interface layer causes the formation of non-ideal Schottky contact between ML graphene and SiC. This is attributed to the presence of a large density of interface states. Mid-infrared optical Hall effect measurements revealed Landau-level transitions in FLG that have a square-root dependence on magnetic field, which evidences a stack of decoupled graphene sheets. Contrary to previous works on decoupled C-face graphene, our BL and FLG are composed of ordered decoupled graphene layers without out-of-plane rotation.

Improved Evaluation Method for Channel Mobility in SiC Trench MOSFETs

We proposed an improved method for evaluating the effective channel mobility (μeff), involving an appropriate definition of the threshold voltage (Vth) based on the ideal gate bias voltage – drain current (VG-ID) characteristics. Using this method, the dependence of μeff on the effective field (Eeff) could be evaluated even for SiC trench MOSFETs with large interface state density (Dit) values. The dominant influence on μeff in the low Eeff region was found to be Coulomb scattering caused by interface states at the SiC/SiO2 interfaces.

Frequency dispersion in III-V metal-oxide-semiconductor capacitors

A recombination-controlled tunneling model is used to explain the strong frequency dispersion seen in the accumulation capacitance and conductance of dielectric/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors. In this model, the parallel conductance is large when, at positive gate biases, the metal Fermi level lines up with a large density of interface states in the In0.53Ga0.47As band gap. It is shown that the model explains in a semi-quantitative manner the experimentally observed capacitor characteristics, including a peak in parallel conductance/frequency (Gp/ω) versus log frequency curves at positive gate bias and the dependence of the frequency dispersion on the dielectric thickness.

Time-of-flight studies on TiO2/CuInS2 heterojunctions

Time-of-Flight (TOF) measurements have been performed on n-type TiO2/p-type CuInS2 heterojunctions. The TiO2 film thickness has been varied between 200 and 400 nm, while the CuInS2 film thickness has been fixed at 500 nm. The TOF response can be accurately modeled, if the potential drop across the p-n heterojunction with a large density of interface states is properly accounted for. Also electron transport in a space-charge region for a not fully depleted semiconductor has to be considered. The electron mobility in TiO2 is found to be 10−2 cm2 V−1 s−1, independent of the TiO2 layer thickness. The interface-state densities are 5×1011, 2×1012, and 6×1012 eV−1 cm−2 for 200, 300, and 400 nm thick TiO2 films, respectively.

Electrical properties of as-grown molecular beam epitaxy high-k gate dielectrics deposited on silicon

The carrier transport mechanisms in as-grown LaAlO3 and La2Hf2O7 high-k insulator layers deposited on n- and p-Si were deduced from temperature dependent C-V and I-V characteristics correlated with photoelectric measurements. Large, parallel shifts in the high frequency C-V curves are explained by the presence of a large density of interface states and an approximate analytical formula relating the density of states to the C-V shift is deduced. The space charge limited current is explained by the existence of impurity channels situated energetically near the conduction or valence band of silicon.

Control of interface states at metal/6H-SiC(0001) interfaces

Metal/$6\mathrm{H}\ensuremath{-}\mathrm{SiC}(0001)$ interfaces free of Fermi level pinning were formed by realizing well-ordered atomic arrangements and perfect termination of the surface atoms of SiC substrates. The surfaces and interfaces were investigated by electrical measurements, Auger electron spectroscopy, low energy electron diffraction, x-ray photoemission spectroscopy, scanning tunneling microscopy, and transmission electron microscopy. We used three different regimes for the surface treatments: (i) the conventional procedure of degreasing and HF dipping, (ii) thermal oxidation followed by HF dipping after (i), and (iii) immersion into boiling water after (ii). We found that the dependence of the Schottky barrier height on the metal work function changes drastically following these surface treatments. The Fermi level at the interface prepared using only treatment (i) was almost pinned at \ensuremath{\sim}0.8 eV below the conduction band minimum. On the other hand, for the interfaces formed by treatments (ii) and (iii), the position of the interface Fermi level varied strongly with the metal work function. In particular, treatment (iii) approached the Schottky limit, with a density of interface states of $4.6\ifmmode\times\else\texttimes\fi{}{10}^{10}{\mathrm{states}\mathrm{\ensuremath{\cdot}}\mathrm{cm}}^{\ensuremath{-}2}\ensuremath{\cdot}{\mathrm{eV}}^{\ensuremath{-}1}.$ The surface characterization of the SiC surfaces formed by the Schottky-limit treatment (iii) indicated that the surface was atomically flat, the terraces of the surface was terminated by hydrogen atoms, and their step-edges were stable due to passivation by oxygen. An abrupt commensurate epitaxial connection at the Ti/SiC interface was found for treatment (iii), whereas the Ti/SiC interface obtained by employing treatment (i) had a disordered layer with a thickness of \ensuremath{\sim}2 nm, which is the origin of the large density of interface states enough to pin the interface Fermi level.

Interfacial properties of single-crystalline CeO2 high-k gate dielectrics directly grown on Si (111)

Interfacial properties of single-crystalline CeO2 high-k dielectrics directly grown on Si (111) were investigated by comparing metal–insulator–semiconductor field-effect transistors (MISFETs) without any interfacial layer [(w/o-IL); direct growth of CeO2 on Si] and those with an interfacial layer (w-IL). FET characteristics, such as the drain current and the S factor, for the w/o-IL MISFET were much worse than those for the w-IL MISFET. The in-gap states attributed to the oxygen defects were detected in the CeO2 directly grown on Si by x-ray photoelectron spectroscopy measurements. The large interface state density induced by the oxygen defects at the CeO2/Si interface may deteriorate the w/o-IL MISFET performances.

High frequency CV measurements of SiC MOS capacitors

MOS capacitors have been fabricated on a p-type 6H–SiC substrate with 〈0001〉Si orientation. The oxide was thermally grown under wet conditions. High frequency CV measurements have been carried out with different sweep rates and stress times in darkness and under different illumination conditions. The bump which appears in the CV curves is most likely a 6H–SiC manifestation of nonequilibrium effects. A hook which occurs in deep depletion when the structure is measured with UV light is observed. The density of states has been determined using the Terman method and the conductance technique including band bending fluctuations. Due to nonequilibrium effects in the semiconductor occurring during CV measurements, the Terman method induces errors in the extraction of the interface trap density of SiC MOS devices. The low value of the standard deviation of the surface potential was assumed to be rather due to the large interface state density than to an improvement of the SiC/SiO 2 interface. The extracted D it values at the SiC/SiO 2 interface are in the range of 10 12 cm −2 eV −1, similar to those available in literature for this oxidation temperature.

Interfaces of InAsP/InP multiple quantum wells grown by metalorganic vapor phase epitaxy

We present results of the growth of InAsxP1−x/InP strained heterostructures by low pressure metalorganic vapor phase epitaxy. A large incorporation of arsenic into the InAsP ternary was observed using tertiarylbutylarsine as precursor. High resolution x-ray diffraction, photoluminescence, and optical absorption measurements for InAsP/InP strained multiple quantum wells reveal that the InAsP/InP interface is very sensitive to growth interruption. A systematic study of a growth in terruption sequence designed to improve the InAs/InP interface was carried out. For nonoptimal growth interruption procedures a large density of interface states is created, probably as a consequence of compositional modifications within the interface region. We find that the absorption spectrum may reveal a significant density of interface states. Thus, photoluminescence on its own is insufficient to characterize the interface roughness even for structures showing narrow low-temperature photoluminescence peaks. We also observe an enhancement of the As content for structures grown on InP (001) relative to those simultaneously grown on InP(001) two degrees off toward [100], which suggests that the composition of As in the ternary is limited by its surface diffusion.

The Effect of Growth Interruption on Structural and Optical Properties of InAsP/InP Multiple Quantum Wells

A systematic study of the effect of growth interruption on the interface roughness of InAsxPi1−x/InP heterostructures has been carried out. High resolution X-ray diffraction, photoluminescence and optical absorption measurements for InAsP/InP strained multiple quantum wells reveal that the InAsP/InP interface is very sensitive to growth interruption. For nonoptimal growth interruption procedures a large density of interface states is created, probably as a consequence of compositional modifications within the interface region. We find that photoluminescence on its own is insufficient to characterize the interface roughness in our samples, since even for narrow low-temperature peak emissions corresponding to the multiple quantum wells, the absorption spectrum may reveal a significant density of interface states.

Growth and characterization of InAs microclusters in InP and InAsP/InP heterostructures by low pressure MOCVD using tertiarybutylarsine

InAs microclusters embedded in an InP matrix and InAs x P 1– x /InP (0.1 ≤ x≤0.3) strained multiple quantum wells (SMQW) have been prepared by LP-MOCVD using tertiarybutylarsine (TBAs) as a substitute for AsH 3. The relatively large cracking efficiency of TBAs resulted in low As/In ratios (from 4.3 to 8.8) for InAs/InP structures and low As/P ratios (from 1×10 -3 to 3.5×10 -3 for InAs x P 1– x /InP (0.1 ≤ x ≤0.3). High-resolution X-ray diffraction (HRXRD) and photoluminescence (PL) show that the TBAs-grown material is of high quality. The HRXRD patterns of InAs microclusters embedded in the InP matrix demonstrate that the InAs unit cell is tetragonally distorted in accordance with the elasticity theory. For InAs microclusters embedded in the InP matrix, the 7 K emission PL peak shifts from 1.35 to 1.39 eV when the InAs coverage is reduced from 0.8 to 0.2 monolayers, a clear indication of a lateral size effect. Picosecond time resolved PL shows a weak coupling of excitons confined by these InAs microclusters. We report also the results of a study of the interface roughness of InAs x P 1– x /InP heterostructures. HRXRD, PL, absorption and photoconductivity (PC) measurements for InAsP/InP SMQW reveal that the InAsP/InP interface is very sensitive to growth procedure. For nonoptimal growth procedures a large density of interface states is created, probably as a consequence of compositional modifications within the interface region. The optical measurements clearly resolve the fundamental intersubband transitions in the InAsP/InP SMQW, including heavy hole-light splittings, even at room temperature.

Photoreflectance study of electric field distributions in semiconductors heterostructures grown on semi-insulating substrates

We have studied the photoref lectance (PR) spectra from a MBE grown heterostructure consisting of 200 nm of Ga0.83Al0.17As, a 800 nm GaAs buffer layer on a semi-insulating (100) LEC GaAs substrate. By varying both the pump beam wavelength and modulation frequency (up to 100 kHz) we are able to identify the component layers, their quality and the properties of the various interfaces. In this study we find evidence for a low density of interface states between the GaAs buffer layer and GaAlAs layer and a relatively large density of interface states between the substrate and buffer regions. These states, previously observed by Deep Level Transient Spectroscopy of doped structures, are presumably associated with the interface produced by MBE growth on etched and air exposed substrates. However, in our material, since the substrate is semi-insulating and the buffer layer is undoped, it is difficult to resolve these states spatially by C-V techniques. Our results show that the PR technique can be used to characterize low conductivity or semi-insulating structures such as enhancement mode MESFET and HEMT type devices and it may be useful for the in-situ characterization of epigrown surfaces and interfaces

Electric field distributions in a molecular-beam epitaxy Ga0.83Al0.17As/GaAs/GaAs structure using photoreflectance

We have studied the photoreflectance (PR) spectra from a molecular-beam epitaxially (MBE) grown heterostructure consisting of 200 nm of Ga0.83Al0.17As , a 800-nm GaAs buffer layer on a semi-insulating (SI) 〈100〉 (LEC) GaAs substrate. By varying both the pump beam wavelength and modulation frequency we are able to identify the component layers, their quality, and the quality of the various interfaces. In this study we find evidence for a low density of interface states between the GaAs buffer layer and the GaAlAs layer, and a relatively large density of interface states, between the substrate and buffer layers. These states, previously observed by deep-level transient spectroscopy (DLTS) of doped structures, are presumably associated with the interface produced by MBE growth on etched and air exposed substrates. However, in our experiment since the substrate is semi-insulating and the buffer layer is undoped, it is difficult to resolve these states spatially by C–V techniques. Our results show that the PR technique can be used to characterize low conductivity or semi-insulating structures such as enhancement mode metal–semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) type devices and it may be useful for the in situ characterization of epigrown surfaces and interfaces.

The semiconductor/electrolyte interface: A re-examination of n-type Cadmium Telluride electrodes

The behavior of the n-CdTe electrode is re-examined for materials grown by the travelling heater method using Cd as a solvent. Except at pH 14, results appear to differ from those found with classical CdTe. Generally a large density of interface states exists in the potential range from −0.4 to −0.9 V, which leads to a Fermi level pinning process. The influence of redox species on this behavior is checked at pH 0 using oxygen and Fe 2+ Fe 3+ In the first case, a complex mechanism leads to a large density of interface states whereas in the second, the redox couple acts as a stabilizer for the electrode surface. From the point of view of material properties, photoelectrochemical measurements lead to conclude that these CdTe correspond to the best quality CdTe grown by more classical methods.

C‐V Characteristics of Al / SiON / GaAs MIS Systems

Plasma‐enhanced chemical vapor deposited dielectric film on was prepared as the insulator in a metal‐insulator‐semiconductor structure for capacitance‐voltage characteristics analysis. The substrate was pretreated by ammonia plasma prior to the film deposition. The capacitance dispersion, hysteresis, and flatband voltage were discussed as functions of test frequency and bias‐time stress. The frequency dependence of capacitance dispersion and flatband voltage can be attributed primarily to the interface states, whereas the clockwise hysteresis can be explained as the total effects of interface states near midgap and charge injection. The larger deviation of inversion capacitance from ideal values is attributed to the large density of interface states distributed in the lower half of the energy gap. An interface state density distribution model was proposed to explain the capacitance‐voltage characteristics of systems.

Electrical properties of ( p)Te-( p)Si isotype heterojunction

The ( p) tellurium-( p) silicon heterojunction has been prepared by vacuum evaporation of tellurium (Te) films on silicon (Si) substrates. The influence of the thickness (1000–13000 Å) and annealing on the electrical properties of the films and heterojunction properties have been investigated. The films prepared on heated substrates (∼425 K) show the properties of the annealed films and good adherance on Si substrates. The current-voltage (I-V) characteristics of the ( p)Te-( p)Si heterojunction have been studied in the temperature range 77 to about 360 K. The I-V characteristics show a double saturation indicating the applicability of double Schottky diode model for isotype heterojunctions when large density of interface states (∼1014) are present. The film thickness and resistivity of the Si (0.4–11 Ω cm) show little influence on the I-V characteristics or builtin potential estimated from the temperature dependence of I-V characteristics. In spite of large difference in band gap of Si and Te the estimated builtin potential on Si (VD1) is only slightly higher than on Te (VD2) side. This suggests that the heterojunction properties are mainly controlled by the interface states. The large interface states in Te-Si heterojunction make the double Schottky diode model valid even when the carrier concentration of Te is more than three orders of magnitude higher than that of Si.

Effects of bombardment by low-energy neutral particles on silicon dioxide films

Ion bombardment or backsputtering of SiO2 films has been shown to result in severe insulator degradation in device processing. Here we have investigated the effects of low-energy neutral-particle bombardment on device quality SiO2 films and have compared degradation produced by neutral-particle bombardment with that produced by ion bombardment. These results show that (1) neutral-particle bombardment produces substantially less (by two or three orders of magnitude) fixed charge at the SiO2/Si interface than does ion bombardment; (2) the most prominent degradation produced by neutral bombardment is the creation of a large interface state density across the band gap which is not related to a nonuniform charge distribution at the interface; (3) metal-oxide-semiconductor degradation produced by neutral bombardment may be removed by annealing at temperatures ?400 °C. Comparison of oxide charge degradation produced in SiO2 by ion and neutral-particle bombardment suggests that the neutralization processes at the vacuum-SiO2 interface, which take place only in ion bombardment, have the dominant role in this degradation. As a result of these processes, in ion bombarded samples, charge carriers migrate to the SiO2/Si interface in the field across the oxide film. This mechanism is absent in the case of neutral bombardment.