Large Cache Research Articles

Implications of gated-Vss technique on leakage power in embedded caches

In this study, we designed and implemented the gated-Vss technique on a wide range of embedded workloads and evaluated the effects of varying parameters on the static power, specifically for caches (180,130,100, and 70 nm technology nodes with a customised simulator.) The static power increased by 50% when the cache sizes were increased from 16k to 128k for L1 cache and 256k to 2M for L2 cache. Gated-Vss is an ideal solution for larger caches, especially with small latencies. Our results also indicate that the static power savings are higher when the embedded systems have dense memory operations and less misprediction rates.

Phytochemical and genetic analyses of ancient cannabis from Central Asia

The Yanghai Tombs near Turpan, Xinjiang-Uighur Autonomous Region, China have recently been excavated to reveal the 2700-year-old grave of a Caucasoid shaman whose accoutrements included a large cache of cannabis, superbly preserved by climatic and burial conditions. A multidisciplinary international team demonstrated through botanical examination, phytochemical investigation, and genetic deoxyribonucleic acid analysis by polymerase chain reaction that this material contained tetrahydrocannabinol, the psychoactive component of cannabis, its oxidative degradation product, cannabinol, other metabolites, and its synthetic enzyme, tetrahydrocannabinolic acid synthase, as well as a novel genetic variant with two single nucleotide polymorphisms. The cannabis was presumably employed by this culture as a medicinal or psychoactive agent, or an aid to divination. To our knowledge, these investigations provide the oldest documentation of cannabis as a pharmacologically active agent, and contribute to the medical and archaeological record of this pre-Silk Road culture.

Caches for Multimedia Workloads: Power and Energy Tradeoffs

One of the significant workloads in current generation desktop processors and mobile devices is multimedia processing. Large on-chip caches are common in modern processors, but large caches will result in increased power consumption and increased access delays. Regular data access patterns in streaming multimedia applications and video processing applications can provide high hit-rates, but due to issues associated with access time, power and energy, caches cannot be made very large. Characterizing and optimizing the memory system is conducive for designing power and performance efficient multimedia application processors. Performance tradeoffs for multimedia applications have been studied in the past, however, power and energy tradeoffs for caches for multimedia processing have not been adequately studied in the past. In this paper, we characterize multimedia applications for I-cache and D-cache power and energy using a multilevel cache hierarchy. Both dynamic and static power increase with increasing cache sizes, however, the increase in dynamic power is small. The increase in static power is significant, and becomes increasingly relevant for smaller feature sizes. There is significant static power dissipation, ~ 45%, in L1 & L2 caches at 70 nm technology sizes, emphasizing the fact that future multimedia systems must be designed by taking leakage power reduction techniques into account. The energy consumption of on-chip L2 caches is seen to be very sensitive to cache size variations. Sizes larger than 16 k for I-caches and 32 k for D-caches will not be efficient choices to maintain power and performance balance. Since multimedia applications spend significant amounts of time in integer operations, to improve the performance, we propose implementing low power full adders and hybrid multipliers in the data path, which results in 9% to 21% savings in the overall power consumption.

Personalized satellite‐based audio and multimedia services for vehicular terminals

AbstractThis paper presents the personalized satellite radio, a novel satellite‐based radio concept, capable of providing radio services to vehicular terminals. This paper describes the technical solution proposed, which overcomes the classical streaming approach used for traditional radio. The main concept behind it is that individual audio and multimedia files are broadcast to the mobile users instead of transmitting a number of continuous streams. The received files are stored in a large cache located in the receiver of each mobile terminal and are sequentially played to generate a service similar to traditional radio/entertainment programmes. The resulting file‐based radio approach makes, in particular, use of higher‐layer coding at the transport layer and smart techniques to build up an audible programme with no interruptions and full audio quality based on the available files. This paper also presents the results of extensive trials that were conducted with a system prototype developed in the framework of an European Space Agency funded project. Copyright © 2008 John Wiley & Sons, Ltd.

On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures

The benefits and deficiencies of shared and private caches have been identified by researchers. The performance impact of privatizing or sharing caches on homogeneous multi-core architectures is less understood. This paper investigates the performance impact of cache sharing on a homogeneous same-ISA 16-core processor with private first-level (L1) caches by considering 3 cache models which vary the sharing property of second-level (L2) and third-level (L3) cache banks. It is observed that across many scenarios, the cache privatization’s average memory access time improved as the L1 cache miss rate increased and/or the cross-partition interconnect latencies increased. Under uniform memory address distribution, and when the L3 cache miss rate is close to 0, privatizing both L2s and L3s performs best among the 3 cache models. Furthermore, we mathematically demonstrate that when the interconnect’s bridge latency is below 264 cycles, privatizing L2 caches beats privatizing both L2 and L3 caches, while the reverse is true for large bridge latencies representing high-traffic and heavy workload applications. For large interconnect delays, the private L2 and L3 model is best. For low to moderate interconnect latencies, and when the L3 miss rate is not close to 0, sharing both L2 and L3 banks among all cores performs best followed by privatizing L2s, while privatizing both L2s and L3s ranks last. Under worst case address distributions, cache privatizing benefits generally increase, and with large bridge latencies, privatizing L2 and L3 banks outperforms the other cache models. This reveals that as application workloads become heavier with time, resulting in large cache miss rates and long bridge and interconnect delays, privatizing L2 and L3 caches may prove beneficial. Under less stressful workloads, sharing both L2 and L3 caches have the upper hand. This study confirms the desired configurability and flexibility of the cache memory’s sharing degree based on the running workload.

Performance of commercial multimedia workloads on the Intel Pentium 4: A case study

In this paper, we present a case study of the execution time characteristics of several popular commercial audio and video applications on a state of the art microprocessor, the Intel Pentium 4. The on-chip performance counters on the Pentium 4 processor are used to perform this study using actual real-world workloads. While the Pentium 4 is capable of executing 3–4 instructions in one cycle, it was observed that commercial audio and video applications take between 1.4 and 3.5 cycles (per instruction) to execute. Despite using large caches and sophisticated out of ordering techniques, the average cycles per instruction is higher than a predecessor like Pentium II. This indicates that while clock frequency has improved, real speedups are not scaling. The performance of multimedia programs is compared with execution characteristics of SPEC CPU 2000 programs. Performance impact of branch predictors, caches and trace caches on the Pentium 4 are analyzed for multimedia and SPEC CPU applications.

The persistent‐access‐caching algorithm

AbstractCaching is widely recognized as an effective mechanism for improving the performance of the World Wide Web. One of the key components in engineering the Web caching systems is designing document placement/replacement algorithms for updating the collection of cached documents. The main design objectives of such a policy are the high cache hit ratio, ease of implementation, low complexity and adaptability to the fluctuations in access patterns. These objectives are essentially satisfied by the widely used heuristic called the least‐recently‐used (LRU) cache replacement rule. However, in the context of the independent reference model, the LRU policy can significantly underperform the optimal least‐frequently‐used (LFU) algorithm that, on the other hand, has higher implementation complexity and lower adaptability to changes in access frequencies. To alleviate this problem, we introduce a new LRU‐based rule, termed the persistent‐access‐caching (PAC), which essentially preserves all of the desirable attributes of the LRU scheme. For this new heuristic, under the independent reference model and generalized Zipf's law request probabilities, we prove that, for large cache sizes, its performance is arbitrarily close to the optimal LFU algorithm. Furthermore, this near‐optimality of the PAC algorithm is achieved at the expense of a negligible additional complexity for large cache sizes when compared to the ordinary LRU policy, since the PAC algorithm makes the replacement decisions based on the references collected during the preceding interval of fixed length. © 2008 Wiley Periodicals, Inc. Random Struct. Alg., 2008

A decompression pipeline for accelerating out-of-core volume rendering of time-varying data

This paper presents a decompression pipeline capable of accelerating out-of-core volume rendering of time-varying scalar data. Our pipeline is based on a two-stage compression method that cooperatively uses the CPU and the graphics processing unit (GPU) to transfer compressed data entirely from the storage device to the video memory. This method combines two different compression algorithms, namely packed volume texture compression (PVTC) and Lempel-Ziv-Oberhumer (LZO) compression, allowing us to exploit both temporal and spatial coherence in time-varying data. Furthermore, it achieves fast decompression by taking architectural advantages of each processing unit: a hardware component on the GPU and a large cache on the CPU, each suited to decompress PVTC and LZO encoded data, respectively. We also integrate the method with a thread-based pipeline mechanism to increase the data throughput by overlapping data loading, data decompression, and rendering stages. Our pipelined renderer runs on a quad-core PC and achieves a video rate of 41 frames per second (fps) in average for 258x258x208 voxel data with 150 time steps. It also demonstrates an almost interactive rate of 8fps for 512x512x295 voxel data with 411 time steps.

Architecting Efficient Interconnects for Large Caches with CACTI 6.0

Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. an enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. the new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

Optimising a 3D multigrid algorithm for the IA-64 architecture

Multigrid methods are amongst the most efficient algorithms to numerically solve partial differential equations. However, standard implementations usually cannot exploit the potential of modern processors. The IA-64 architecture transferes most complexity to the software side to provide a highly superscalar design with large caches, leading to unique control over the actual execution. Exemplified on a simple multigrid solver equation in 3D and the Itanium 2 processor, we present how known performance optimisation techniques can be successfully combined. While implementation details are specific, the optimisation concept should be applicable for a wide range of numerical algorithm and CPUs.

The causes of bloat, the limits of health

Applications often have large runtime memory requirements. In some cases, large memory footprint helps accomplish an important functional, performance, or engineering requirement. A large cache,for example, may ameliorate a pernicious performance problem. In general, however, finding a good balance between memory consumption and other requirements is quite challenging. To do so, the development team must distinguish effective from excessive use of memory. We introduce health signatures to enable these distinctions. Using data from dozens of applications and benchmarks, we show that they provide concise and application-neutral summaries of footprint. We show how to use them to form value judgments about whether a design or implementation choice is good or bad. We show how being independent ofany application eases comparison across disparate implementations. We demonstrate the asymptotic nature of memory health: certain designsare limited in the health they can achieve, no matter how much the data size scales up. Finally, we show how to use health signatures to automatically generate formulas that predict this asymptotic behavior, and show how they enable powerful limit studies on memory health.

Interconnect design considerations for large NUCA caches

The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposals advocate splitting the cache into a large number of banks and employing a network-on-chip (NoC) to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures--NUCA). Most studies on NUCA organizations have assumed a generic NoC and focused on logical policies for cache block placement, movement, and search. Since wire/router delay and power are major limiting factors in modern processors, this work focuses on interconnect design and its influence on NUCA performance and power. We extend the widely-used CACTI cache modeling tool to take network design parameters into account. With these overheads appropriately accounted for, the optimal cache organization is typically very different from that assumed in prior NUCA studies. To alleviate the interconnect delay bottleneck, we propose novel cache access optimizations that introduce heterogeneity within the inter-bank network. The careful consideration of interconnect choices for a large cache results in a 51% performance improvement over a baseline generic NoC and the introduction of heterogeneity within the network yields an additional 11-15% performance improvement.

Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production

Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.

Exploiting client caches to build large Web caches

New demands brought by the continuing growth of the Internet will be met in part by more effective and comprehensive use of caching. This paper proposes to exploit client browser caches in the context of cooperative proxy caching by constructing the client caches within each organization (e.g., corporate networks) as a peer-to-peer (P2P) client cache. Via trace-driven simulations we evaluate the potential performance benefit of cooperative proxy caching with/without exploiting client caches. We show that exploiting client caches in cooperative proxy caching can significantly improve performance, particularly when the size of individual proxy caches is limited compared to the universe of Web objects. We further devise a cooperative hierarchical greedy-dual replacement algorithm (Hier-GD), which not only provides some cache coordination but also utilizes client caches. Through Hier-GD, we explore the design issues of how to exploit client caches in cooperative proxy caching to build large Web caches. We show that Hier-GD is technically practical and can potentially improve the performance of cooperative proxy caching by utilizing client caches.

Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates

Cache miss rates are an important subset of system model inputs. Cache miss rate models are used for broad design space exploration in which many cache configurations cannot be simulated directly due to limitations of trace collection setups or available resources. Often it is not practical to simulate large caches. Large processor counts and consequent potentially high degree of cache sharing are frequently not reproducible on small existing systems. In this article, we present an approach to building multivariate regression models for predicting cache miss rates beyond the range of collectible data. The extrapolation model attempts to accurately estimate the high-level trend of the existing data, which can be extended in a natural way. We extend previous work by its applicability to multiple miss rate components and its ability to model a wide range of cache parameters, including size, line size, associativity and sharing. The stability of extrapolation is recognized to be a crucial requirement. The proposed extrapolation model is shown to be stable to small data perturbations that may be introduced during data collection.We show the effectiveness of the technique by applying it to two commercial workloads. The wide design space contains configurations that are much larger than those for which miss rate data were available. The fitted data match the simulation data very well. The various curves show how a miss rate model is useful for not only estimating the performance of specific configurations, but also for providing insight into miss rate trends.

PicoServer

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that thermal constraints, a concern with 3D stacking, are easily satisfied.The PicoServer architecture specifically targets Tier 1 server applications, which exhibit a high degree of thread level parallelism. An architecture targeted to efficient throughput is ideal for this application domain. We find for a similar logic die area, a 12 CPU system with 3D stacking and no L2 cache outperforms an 8 CPU system with a large on-chip L2 cache by about 14% while consuming 55% less power. In addition, we show that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power, even when conservative assumptions are made about the power consumption of the PicoServer.

PicoServer

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that thermal constraints, a concern with 3D stacking, are easily satisfied.The PicoServer architecture specifically targets Tier 1 server applications, which exhibit a high degree of thread level parallelism. An architecture targeted to efficient throughput is ideal for this application domain. We find for a similar logic die area, a 12 CPU system with 3D stacking and no L2 cache outperforms an 8 CPU system with a large on-chip L2 cache by about 14% while consuming 55% less power. In addition, we show that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power, even when conservative assumptions are made about the power consumption of the PicoServer.

PicoServer

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that thermal constraints, a concern with 3D stacking, are easily satisfied.The PicoServer architecture specifically targets Tier 1 server applications, which exhibit a high degree of thread level parallelism. An architecture targeted to efficient throughput is ideal for this application domain. We find for a similar logic die area, a 12 CPU system with 3D stacking and no L2 cache outperforms an 8 CPU system with a large on-chip L2 cache by about 14% while consuming 55% less power. In addition, we show that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power, even when conservative assumptions are made about the power consumption of the PicoServer.

Memory performance prediction for high-performance microprocessors at deep submicrometer technologies

The desire for large size, high-speed, and low-power on-chip memory necessitates early and accurate estimates of memory performance. A new performance model as well as an early cache design tool and predictor of access and cycle time for cache stack (PRACTICS) has been developed for on-chip static random access memory (SRAM) cache design that includes both delay and dynamic-power models. Efficient models for distributed interconnect delays, verified by Cadence simulations, are introduced, and their necessity is demonstrated. In the delay model, the access time is estimated by decomposing each component into several equivalent lumped resistance-capacitance (RC) circuits and using an appropriate order pi model to approximate the distributed wire delays of each stage. The dynamic-power model calculates the charging power dissipation of the load capacitances using the same equivalent lumped RC circuits. The delay model has been validated with an Intel 18-Mb SRAM at the 180-nm node, achieving accuracy to within 10% of the measured results. The dynamic-power model has been validated with an International Business Machines Corporation (IBM) 18-Mb SRAM at the 180-nm node, to within 13% of the measured power consumption. Detailed comparisons between PRACTICS and cache access and cycle time model (CACTI) in both validation cases indicate that an improved wire delay, appropriate circuit structures, and technology dependent parameters are necessary to accurately predict large cache memory performance at deep submicrometer technology nodes. PRACTICS is used to analyze the access time and power consumption in terms of cache sizes and various degrees of associativity for architectural studies. In addition, the PRACTICS simulation results show that repeater insertion reduces the access time significantly, with a small overhead in dynamic-power consumption for large size cache design at deep submicrometer technology

Occurrence of Cordaitales from lower Gondwana sediments of Ib-River Coalfield, Orissa, India: An Indian scenario

The Ib-River Coalfield in Orissa State is a part of Mahanadi Master Basin. Recent extensive investigations were conducted in this Coalfield to locate fossiliferous beds in the Lower Gondwana deposits and as a result a large cache of plant fossils were recovered from Lower Permian sediments (Barakar Formation) exposed in Jurabaga and Lajkura Collieries. The complete flora includes 23 genera representing nine orders viz., Lycopodiales, Equisetales, Sphenophyllales, Filicales, Cordaitales, Coniferales, Ginkgoales, Cycadales and Glossopteridales. Only the Cordaitales, represented by four genera i.e., Noeggerathiopsis, Cordaites, Euryphyllum and Kawizophyllum are discussed in this paper. Cordaitalean leaves are described for the first time from this coalfield; the remaining plant groups will be considered in a subsequent publication. Cordaitalean leaves attributable to Noeggerathiopsis hislopii, Noeggerathiopsis minor, Euryphyllum whittianum, Euryphyllum maithyi, Kawizophyllum dunpathriensis and Cordaites sp. constitute about 13.90% (111 specimens) of the total plant assemblage collected from this Coalfield. Of the cordaitaleans, N. hislopii is most abundant (47.75%; 53 specimens) followed by E. whittianum (40.54%; 45 specimens). A summary of the distribution of Cordaitales throughout the Indian Gondwana is also presented. Floristic composition varies stratigraphically at the two Barakar exposures (Lajkura and Jurabaga Collieries). Cordaitales are preserved only in the lowermost (4th) horizon (lower floral zone). Strata in these collieries have been assigned to the lower and upper Barakar Formation based on floristic content and an Early Permian (Artinskian) age is assigned.