Large Area Si Substrates Research Articles

Light-Emitting Diodes Based on InGaN/GaN Nanowires on Microsphere-Lithography-Patterned Si Substrates.

The direct integration of epitaxial III-V and III-N heterostructures on Si substrates is a promising platform for the development of optoelectronic devices. Nanowires, due to their unique geometry, allow for the direct synthesis of semiconductor light-emitting diodes (LED) on crystalline lattice-mismatched Si wafers. Here, we present molecular beam epitaxy of regular arrays n-GaN/i-InGaN/p-GaN heterostructured nanowires and tripods on Si/SiO2 substrates prepatterned with the use of cost-effective and rapid microsphere optical lithography. This approach provides the selective-area synthesis of the ordered nanowire arrays on large-area Si substrates. We experimentally show that the n-GaN NWs/n-Si interface demonstrates rectifying behavior and the fabricated n-GaN/i-InGaN/p-GaN NWs-based LEDs have electroluminescence in the broad spectral range, with a maximum near 500 nm, which can be employed for multicolor or white light screen development.

Magnetotransport and ARPES studies of the topological insulators Sb2Te3 and Bi2Te3 grown by MOCVD on large-area Si substrates

Recently, the topological insulators (TIs) antimony telluride (Sb2Te3) and bismuth telluride (Bi2Te3) are attracting high interest for applications based on spin-charge interconversion mechanisms. Aiming to make a step toward the technology transfer, it is of major importance to achieve and investigate epitaxial quality-TIs on large area Si-based substrates. In view of that, we report here magnetotransport and angle-resolved photoemission spectroscopy (ARPES) studies on Sb2Te3 and Bi2Te3 thin films grown by metal organic chemical vapor deposition (MOCVD) on top of 4″ Si(111) substrates. Clear weak antilocalization (WAL) effects are observed in both TIs, proving the existence of quantum transport mechanism, and the data are successfully interpreted in the framework of the Hikami–Larkin–Nagaoka model. Further, by dedicated magnetotransport experiments, it has been confirmed that the investigated WAL originates from two-dimensional (2D) topological states. ARPES has been performed ex-situ, and in both TIs the gapless Dirac cones have been observed and attributed to the topological surface states. Combining the proofs of the existence of quantum 2D transport as deduced from the analysis of the magnetoconductance curve with the direct observation of the Dirac-like band structure revealed by the ARPES spectra, it is possible to unambiguously confirm the topological nature of our Sb2Te3 and Bi2Te3 thin films. The results obtained on thin films grown by MOCVD on 4’’ Si(111) substrate mark an important step towards the technology transfer of the topological insulators studied in this work.

Spray deposited TiO2 thin films for large-area TiO2/p-Si heterojunction solar cells

Carrier selective contacts (CSC) have the potential to lower the cost of photovoltaic (PV) cells. In the present work p-Si/TiO2 heterojunction solar cells have been fabricated using titanium dioxide (TiO2) as an electron-selective layer. Thin uniform anatase TiO2 films have been deposited using a commercially viable spray deposition technique over large area Si substrates. With a simple architecture of Al (200 nm fingers)/Al (15 nm thin film)/TiO2/c-Si(p)/Ag (200 nm), a highest conversion efficiency of 1.56% has been achieved for the TiO2 carrier selective contact based solar cell with an active area of ∼3.84 cm2. The minority carrier lifetime value of the TiO2 coated Si wafer was found to be less than that of the uncoated wafer, indicating the inability of the anatase TiO2 layer to provide surface passivation. Suns-VOC measurements yielded comparable values of the implied open circuit voltage for both the uncoated and the TiO2 coated Si wafers. Spray deposition technique can be used for scalable fabrication of carrier selective contact based heterojunction solar cells.

Large Spin‐to‐Charge Conversion at Room Temperature in Extended Epitaxial Sb2Te3 Topological Insulator Chemically Grown on Silicon

AbstractSpin‐charge interconversion phenomena at the interface between magnetic materials and topological insulators (TIs) are attracting enormous interest in the research effort toward the development of fast and ultra‐low power devices for future information and communication technology. A large spin‐to‐charge (S2C) conversion efficiency in Au/Co/Au/Sb2Te3/Si(111) heterostructures based on Sb2Te3 TIs grown by metal–organic chemical vapor deposition on 4″ Si(111) substrates is reported. By conducting room temperature spin pumping ferromagnetic resonance, a 250% enhanced charge current due to spin pumping in the Sb2Te3‐containing system is measured when compared to the reference Au/Co/Au/Si(111). The corresponding inverse Edelstein effect length λIEE ranges from 0.28 to 0.61 nm, depending on the adopted methodological analysis, with the upper value being so far the largest observed for the second generation of 3D chalcogenide‐based TIs. These results open the path toward the use of chemical methods to produce TIs on large area Si substrates and characterized by highly performing S2C conversion, thus marking a milestone toward future technology‐transfer.

Current Transport Mechanisms in Au-Free Metallizations for CMOS Compatible GaN HEMT Technology

Gallium nitride (GaN) and its AlGaN/GaN heterostructures grown on large area Si substrates are promising systems to fabricate power devices inside the existing Si CMOS lines. For this purpose, however, Au-free metallizations are required to avoid cross contaminations. In this paper, the mechanisms of current transport in Au-free metallization on AlGaN/GaN heterostructures are studied, with a focus on non-recessed Ti/Al/Ti Ohmic contacts. In particular, an Ohmic behavior of Ti/Al/Ti stacks was observed after an annealing at moderate temperature (600°C). The values of the specific contact resistance ρc decreased from 1.6×104 Ω.cm2 to 7×105 Ω.cm2 with increasing the annealing time from 60 to 180s. The temperature dependence of ρc indicated that the current flow is ruled by a thermionic field emission (TFE) mechanism, with barrier height values of 0.58 eV and 0.52 eV, respectively. Finally, preliminary results on the forward and reverse bias characterization of Au-free tungsten carbide (WC) Schottky contacts are presented. This contact exhibited a barrier height value of 0.82 eV.

Fabrication of group IV semiconductor alloys on Si substrate applying Al paste with screen-printing

We investigated the influence of Sn and Ge ratio in Al paste to fabricate Si-based alloy semiconductor on large-area Si substrate using a conventional screen-printing process and high-temperature treatment steps. From the X-ray diffraction patterns, crystalline SiSn peaks with applying Al-Sn paste have been detected and Sn content in the SiSn layer was estimated around 0.35%, close to the level of solid solubility of Sn in Si. In addition, the Sn depth profile showed similar behavior with Al, which confirms the concept of a liquid epitaxial growth using Al. On the other hand, the SiGe peaks with applying Al–Sn–Ge paste were clearly observed and their main peaks were shifted to a higher angle linearly with decreasing the Ge ratio in the paste. It was suggested that Sn was segregated easily to the surface if in coexistence with Ge due to its lower solubility in SiGe systems.

Fabrication of Si1-xSnx Layer on Si Substrate by Screen-Printing of Al-Sn Paste

Single-crystalline Si1-xSnx thick layers on large area Si substrates are fabricated by applying Al-Sn paste using conventional screen-printing process and high temperature treatment step. The impact of the Al and Sn ratio in the Al-Sn pastes are investigated. From the XRD patterns, the crystalline Si1-xSnx peak has been detected and the Sn content in the Si1-xSnx films is increased with increasing annealing temperature reaching approximately 0.35% at 900°C.

Fabrication of Si1-xGex layer on Si substrate by Screen-Printing

AbstractThe impact of the Al and Ge ratio in the Al-Ge pastes are investigated for fabricating the single crystalline Si1-xGex thick layers on large area Si substrates by screen-printing metallization process. From X-ray reciprocal space maps, Ge fraction in the fabricated Si1-xGex thick layers are found to increase up to 40% with increasing the Ge ratio in the Al-Ge pastes. On the other hand, the interface of the Si and Si1-xGex layers are getting winding with increasing the Ge ratio in the Al-Ge pastes. The Al-Si-Ge phase diagram indicated that uniform SiGe layer can be fabricated by adjusting the Al-Ge ratio in the pastes within the liquid phase region.

Fabrication and characterization of single junction GaAs solar cells on Si with As-doped Ge buffer

A single junction gallium arsenide (GaAs) solar cell on silicon (Si) substrate with energy conversion efficiency of 11.88% under the AM1.5G spectrum at 1 sun intensity without an anti-reflection coating (ARC) has been developed. This development was enabled by utilizing an intermediate, thin arsenic-doped germanium (As-doped Ge) buffer layer. The thin epitaxial Ge layer (< 2µm) grown on the Si substrate created a virtual Ge-on-Si (Ge/Si) substrate for subsequent growth of the GaAs solar cell, providing low threading dislocation density (TDD) of < 5 × 106cm−2. The energy conversion efficiency could be further improved to 16% upon optimizing the ARC and metal coverage. Hence, a manufacturable III-V photovoltaic on a large-area Si substrate has become possible.

(Invited) Bringing III-Vs into CMOS: From Materials to Circuits

High-mobility channel materials such as InGaAs and SiGe alloys are considered to be the leading candidates for replacing strained Si in future low power/high performance logic circuits. However, the integration of InGaAs on Si and the co-integration of InGaAs devices with SiGe devices are extremely challenging. On the one hand, the large lattice mismatch (8 to 10%) and the potential formation of antiphase domains at the polar/non-polar III-V/Si crystalline interface typically hinder the integration of high quality InGaAs crystals on Si. On the other hand, InGaAs and SiGe require very different processing conditions in terms of thermal budgets, dry and wet chemistries, passivation schemes and contacting schemes which complexifies the realization of CMOS circuits. Recently, tremendous progress were achieved as a result of innovation at the material and device levels. Latest technology developments yielded the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line processes in a 2D co-planar configuration. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Furthermore, progress on 3D Monolithic integration showed that this integration scheme not only an opportunity for further density scaling, but it also offers unique advantages for solving the integration of high mobility materials for 3D CMOS and stacking of functional layers on top of standard CMOS circuitry.

Thin-Film-Flip-Chip LEDs Grown on Si Substrate Using Wafer-Level Chip-Scale Package

Demonstrated are visible GaN-based light-emitting diodes (LEDs) on economical large-area Si substrates using an advanced device and packaging architecture to improve optical output power, while reducing manufacturing costs. The process employs thin-film-flip-chip devices and wafer-level chip-scale packages and uses through-Si-via substrate and anisotropic conductive film for bonding. The improved curvature control region is applied in the epitaxial growth of the LED structure on a Si substrate to achieve flat wafers for epitaxial structures at room temperature, which is critical for wafer-level bonding. External quantum efficiency and light-output power at 350 mA increase by $\sim 12$ % compared with those of conventional flip-chip LEDs grown on a sapphire substrate. The devices also show a reverse-bias leakage current failure rate of <10%.

3C-SiC Transistor With Ohmic Contacts Defined at Room Temperature

Among all SiC polytypes, only 3C-SiC has a cubic structure and can be hetero-epitaxial grown on large area Si substrate, thus providing an alternative choice for fabricating cheap wide bandgap power devices. Here, we present a low resistivity ( $\sim 3\times 10^{\mathrm {{-5}}} \Omega ~\cdot $ cm $^{2})$ ohmic contact formed by directly depositing a Ti/Ni metal stack on n-type 3C-SiC without any extra annealing. For the first time, 3C-SiC lateral MOSFETs with as-deposited ohmic contacts were fabricated, and it turned out not only the ohmic contact is free from any interface voids, but also a higher field-effect mobility value ( $\sim 80$ cm $^{\mathrm {{2}}}$ /V $\cdot $ s) was achieved compared with the annealed devices.

AlGaN/GaN High Electron Mobility Transistor Grown and Fabricated on Lattice Matched Metallic Layers

AlGaN/GaN high electron mobility transistors (HEMTs) showed its promising features in high power and high frequency applications such as inverter units in hybrid electric vehicles, advanced radar systems, and satellite-based communication networks with its high density of sheet carrier concentration, high electron mobility, and radiation hardness. In order to lower the cost of HEMTs, larger diameters substrates are needed. Currently, the HEMT structures are grown on non-native sapphire, SiC and Si substrates or on native substrate of vapor phase epitaxy (VPE) GaN wafers. HEMTs grown on sapphire substrate suffer from poor heat dissipation and higher defect density due to the relative larger lattice mismatch to GaN. SiC has a very good thermal conductivity and is less lattice mismatch to GaN, but high quality semi-insulating SiC substrates are quite expensive. Although, Si substrates are fair low cost and available for larger diameter substrates, due to larger lattice mismatch to GaN, it requires to grow thick complex AlGaN buffers prior to the growth of GaN layer to reduce the threading dislocation density. These thick AlGaN layers are very defective and thermal resistive, which will hinder device heat dissipation. VPE grown GaN wafers are limited to 2-3” diameter and very expensive. Recently, it was reported that high quality GaN layers were grown by RF plasma-assisted molecular beam epitaxy (PA-MBE) or metal organic chemical vapor deposition (MOCVD) on high-quality, single crystal ZrTi refractory metal alloys deposited by plasma sputtering on c-plane sapphire and Si substrates. These ZrTi refractory metal alloys are not only lattice match to GaN, but have a similar coefficient of thermal expansion (CTE) as the CTE of GaN [1]. By employing these ZrTi alloys, there is no need to grow thick AlGaN buffer, both photonic and electronic GaN based device structure can be grown on large area Si substrates to achieve low cost GaN based device fabrication. In this work, we have demonstrated AlGaN/GaN HEMTs grown on ZrTi refractory metal alloys, which were deposited on both Si and sapphire substrates. HEMTs with a gate dimension of 1 µm × 100 um were fabricated and characterized. Both dc and rf performance of AlGaN/GaN HEMTs fabricated on the ZrTi metal alloys will be presented. 1. “Epitaxial Growth of High Quality GaN Films on Lattice Matched Metallic Layers”, A.M. Dabiran, F. Machuca, I. De, and R. Weiss, ECS Trans. 66, 113-117 (2015).

Photoelectrochemical reduction of carbon dioxide using Ge doped GaN nanowire photoanodes

We report on the direct conversion of carbon dioxide (CO2) in a photoelectrochemical cell consisting of germanium doped gallium nitride nanowire anode and copper (Cu) cathode. Various products including methane (CH4), carbon monoxide (CO), and formic acid (HCOOH) were observed under light illumination. A Faradaic efficiency of ∼10% was measured for HCOOH. Furthermore, this photoelectrochemical system showed enhanced stability for 6 h CO2 reduction reaction on low cost, large area Si substrates.

Surface Emitting, High Efficiency Near-Vacuum Ultraviolet Light Source with Aluminum Nitride Nanowires Monolithically Grown on Silicon.

To date, it has remained challenging to realize electrically injected light sources in the vacuum ultraviolet wavelength range (∼200 nm or shorter), which are important for a broad range of applications, including sensing, surface treatment, and photochemical analysis. In this Letter, we have demonstrated such a light source with molecular beam epitaxially grown aluminum nitride (AlN) nanowires on low cost, large area Si substrate. Detailed angle dependent electroluminescence studies suggest that, albeit the light is TM polarized, the dominant light emission direction is from the nanowire top surface, that is, along the c axis, due to the strong light scattering effect. Such an efficient surface emitting device was not previously possible using conventional c-plane AlN planar structures. The AlN nanowire LEDs exhibit an extremely large electrical efficiency (>85%), which is nearly ten times higher than the previously reported AlN planar devices. Our detailed studies further suggest that the performance of AlN nanowire LEDs is predominantly limited by electron overflow. This study provides important insight on the fundamental emission characteristics of AlN nanowire LEDs and also offers a viable path to realize an efficient surface emitting near-vacuum ultraviolet light source through direct electrical injection.

Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget

Introduction Recently, lattice matched InAlN/AlN/GaN-on-silicon integration approach has attracted increasing attention due to the availability of high-quality GaN epiwafers with high throughput epitaxial growth on large area Si substrates for applications in power and RF devices with low power consumption [1-2]. Meanwhile, the development of gate-first process is useful to realize future self-aligned transistor structures. Conventional fabrication of InAlN/GaN high electron mobility transistors (HEMTs) or metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) involves gate-last process where high temperature (>800 oC) annealing is required to form Ti/Al/Ni/Au source and drain ohmic contacts [3]. This is a consequence of traditional gate metallization (e.g., Ni/Au) and gate dielectric not being able to survive such a high ohmic annealing temperature. Therefore, the development of good ohmic contacts with a low thermal annealing budget and thermally stable gate dielectric is required to realize the gate-first process integration for InAlN/GaN HEMTs/MOSHEMTs. In the present work, we report the fabrication and characterization of InAlN/GaN MOSHEMTs using a lift-off free, gate-first CMOS compatible process developed at low thermal budget. Experiment The lattice-matched In0.18Al0.82N/AlN/GaN-on-Si (111) HEMT structure used in this experiment is shown schematically in Fig. 1. The MOSHEMT fabrication using a gate-first process started from mesa isolation followed by 20 nm thick LaAlO3 (LAO) deposition using pulsed laser deposition (PLD) with a substrate temperature of 300 oC. Then, W was sputter deposited followed by gate definition using photolithography and dry etching method. Thereafter, Hf/Al/Ta layer was sputter deposited followed by rapid thermal annealing at 600 oC for 60 s in vacuum to form source and drain ohmic contacts. Results and Discussion The contact resistance and contact resistivity of Hf/Al/Ta ohmic contacts, as analyzed from linear transmission line method (LTLM), are found to ~0.60 Ω·mm and 6.7x10-6 Ω·cm2, respectively. At first, the thermal stability and reliability of the LAO gate dielectric upon 600 oC ohmic anneal in vacuum was optimized under several oxygen partial pressures during PLD. Comparison of capacitance-voltage and reverse gate leakage current characteristics of fabricated devices subject to different oxygen partial pressures in the range from 3.1×10-5 Torr to 5×10-3 Torr are shown in Figs. 2(a) and 2(b), respectively. It is found that LAO deposited under an oxygen partial pressure of 2.7×10-4 Torr exhibits the lowest gate leakage and highest accumulation capacitance, predominantly arisen by an increased dielectric permittivity (k~23.2). Finally, the gate-first CMOS compatible MOSHEMTs were fabricated by choosing the above optimized deposition condition for PLD (2.7×10-4 Torr @ 300 oC) of LAO. Devices having gate dimensions of W/L = 2×50/1 μm, gate-to-source distance of Lgs ~ 2 μm, gate-to-drain distance of Lgd ~ 6 μm, were used for DC output and transfer characterizations. The DC output and transfer characteristics are shown in Figs. 3 (a) and (b), respectively. The MOSHEMTs achieve a saturation drain current (Idsat) of 500 mA/mm at zero gate voltage, threshold voltage (Vth) of -12.6 V, maximum extrinsic transconductance (Gmax) of 44 mS/mm and on-resistance (Ron) of ~ 14 Ω/mm. Conclusion In conclusion, a gate-first CMOS compatible process for InAlN/AlN/GaN-on-Si MOSHEMTs fabrication has been developed. A low thermal budget (600 oC) for ohmic annealing is achieved through the use of Hf/Al/Ta source-drain contacts, thus allowing the fabrication of gate-first CMOS compatible MOSHEMTs using LaAlO3 as the gate dielectric as well as for device passivation purpose. The reasonable DC performance demonstrated (Idsat = 500 mA/mm, Gmax = 44 mS/mm, etc.) for a 1 μm gate length shows promising possibility for gate-first process integration of InAlN/GaN-on-Si MOSHEMTs.

III–V Multijunction Solar Cell Integration with Silicon: Present Status, Challenges and Future Outlook

AbstractAchieving high-efficiency solar cells and at the same time driving down the cell cost has been among the key objectives for photovoltaic researchers to attain a lower levelized cost of energy (LCOE). While the performance of silicon (Si) based solar cells have almost saturated at an efficiency of ~25%, III–V compound semiconductor based solar cells have steadily shown performance improvement at ~1% (absolute) increase per year, with a recent record efficiency of 44.7%. Integration of such high-efficiency III–V multijunction solar cells on significantly cheaper and large area Si substrate has recently attracted immense interest to address the future LCOE roadmaps by unifying the high-efficiency merits of III–V materials with low-cost and abundance of Si. This review article will discuss the current progress in the development of III–V multijunction solar cell integration onto Si substrate. The current state-of-the-art for III–V-on-Si solar cells along with their theoretical performance projections is presented. Next, the key design criteria and the technical challenges associated with the integration of III–V multijunction solar cells on Si are reviewed. Different technological routes for integrating III–V solar cells on Si substrate through heteroepitaxial integration and via mechanical stacking approach are presented. The key merits and technical challenges for all of the till-date available technologies are summarized. Finally, the prospects, opportunities and future outlook toward further advancing the performance of III–V-on-Si multijunction solar cells are discussed. With the plummeting price of Si solar cells accompanied with the tremendous headroom available for improving the III–V solar cell efficiencies, the future prospects for successful integration of III–V solar cell technology onto Si substrate look very promising to unlock an era of next generation of high-efficiency and low-cost photovoltaics.

Tunable ion-swelling for nanopatterning of macroscopic surfaces: The role of proximity effects

Ordered surface nanopatterns with different spatial periods and various characters were prepared on silicon surfaces by masked ion irradiation utilizing the local ion-swelling effect. Langmuir–Blodgett (LB) monolayers of hexagonally arranged Stöber silica particles as nanomasks were applied on large area Si substrates during Ar+ or Xe2+ exposure with different fluences. We show that the height and curvature of surface swelling patterns can be tuned by appropriate selection of the particle diameter, ion energy, and ion fluence. It is also revealed that the ion beam-induced anisotropic deformation of the silica mask can be exploited to tailor the surface geometry. We point that, having knowledge on the diameters and average spacing between the silica particles as extrinsic beam spreading factors, and considering the lateral straggling of the bombarding ions in the mask and in the substrate material as intrinsic beam spreading factors, a simple model of the radial fluence distribution can be applied to predict the main features of irradiation-induced surface patterns. The role of proximity effects in the potential use of this easy, fast, wafer-scale nanofabrication method is discussed.

High-Performance MWIR/LWIR Dual-Band 640 × 480 HgCdTe/Si FPAs

HgCdTe grown on large-area Si substrates allows for larger array formats and potentially reduced focal-plane array (FPA) cost compared with smaller, more expensive CdZnTe substrates. The goal of this work is to evaluate the use of HgCdTe/Si for mid-wavelength/long-wavelength infrared (MWIR/LWIR) dual-band FPAs. A series of MWIR/LWIR dual-band HgCdTe triple-layer n-P-n heterojunction (TLHJ) device structures were grown by molecular-beam epitaxy (MBE) on 100-mm (211)Si substrates. The wafers showed low macro-defect density (< 300 cm ―2 ) and was processed into 20-μm-unit-cell 640 x 480 detector arrays which were mated to dual-band readout integrated circuits (ROICs) to produce FPAs. The measured 80-K cutoff wavelengths were 5.5 μm for MWIR and 9.4 μm for LWIR, respectively. The FPAs exhibited high pixel operabilities in each band, with noise equivalent differential temperature (NEDT) operabilities of 99.98% for the MWIR band and 99.6% for the LWIR band demonstrated at 84 K.

Recent advances in GaN transistors for future emerging applications

AbstractIn this paper, recent advances in GaN‐based transistors for power switching and millimeter wave communications are reviewed. These two applications are emerging in addition to the widely developed power amplifiers at microwave frequencies mainly for cellular base stations. Reduction of the fabrication cost is strongly required for power switching GaN transistors, which is enabled by our epitaxial growth technology on large area Si substrates. Another requisite for the application is to achieve normally‐off operation and our novel device structure called Gate Injection Transistors (GIT) enables it with low enough specific on‐resistance (Ron · A) and high drain current. Here, we also present the world highest breakdown voltage of 10400 V in AlGaN/GaN HFETs, extracting full advantage of the high breakdown strength of GaN. The used poly AlN passivation works as a surface heat spreader with its high thermal conductivity, which effectively relieves the channel temperature resulting in lower thermal resistances. The GaN device for future millimeter wave communication consists of MIS‐type gate using so‐called “in‐situ” deposited SiN as a gate insulator, which exhibits high fmax of 203 GHz and low noise figure of 1.4 dB at 28 GHz. The presented GaN transistors are promising for the two future emerging applications demonstrating high enough potential of the material systems. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)