Ladder Circuit Research Articles

Electrical Resistivity Measurements of Layer Number Determined Multilayer Graphene Wiring for Future Large Scale Integrated Circuit Interconnects

To investigate the feasibility of nanocarbon interconnects for future LSIs, the electrical resistance of exfoliated multilayer graphene (MLG) wirings has been studied with accurate measurements of the number of layers. We employed transmission electron microscopy (TEM) as an exact number determination method, atomic force microscopy (AFM) as a simple method, and an extended optical contrast method as an easy distinction method, which we proposed for determining the number of layers. The sheet resistance of MLG wirings, including TEM determined 3-, 54-, and 341-layer MLGs, has been measured using the four-probe method and the layer number dependence of sheet resistance was discussed on the basis of a ladder circuit model simulation. It is shown that the dependence agrees well with the simulations, suggesting parallel conduction in MLG wirings, even if the probe electrodes are deposited just on the top layer of MLG.

Experimental Evidence of Variable-Order Behavior of Ladders and Nested Ladders

The experimental study of two kinds of electrical circuits, a domino ladder and a nested ladder, is presented. While the domino ladder is known and already appeared in the theory of fractional-order systems, the nested ladder circuit is presented in this article for the first time. For fitting the measured data, a new approach is suggested, which is based on using the Mittag-Leffler function and which means that the data are fitted by a solution of an initial-value problem for a two-term fractional differential equation. The experiment showed that in the frequency domain the domino ladder behaves as a system of order 0.5 and the nested ladder as a system of order 0.25, which is in perfect agreement with the theory developed for their design. In the time domain, however, the order of the domino ladder is changing from roughly 0.5 to almost 1, and the order of the nested ladder is changing in a similar manner, from roughly 0.25 to almost 1; in both cases, the order 1 is never reached, and both systems remain the systems of non-integer order less than 1. Both studied types of electrical circuits provide the first known examples of circuits, which are made of passive elements only and which exhibit in the time domain the behavior of variable order.

A Design Example of a Fractional-Order Kerwin–Huelsman–Newcomb Biquad Filter with Two Fractional Capacitors of Different Order

Design, realization and performance studies of continuous-time fractional order Kerwin–Huelsman–Newcomb (KHN) biquad filters have been presented. The filters are constructed using two fractional order capacitors (FC) of orders α and β (0<α, β≤1). The frequency responses of the filters, obtained experimentally have been compared with simulated results using MATLAB/SIMULINK and also with PSpice (Cadence PSD 14.2), where the fractional order capacitor is approximated by a domino ladder circuit. It has been observed that fractional order filters can give better performance in certain aspects compared to integer order filters. The effects of the exponents (α and β) on bandwidth and stability of the realized filter have been examined. Sensitivity analysis of the realized fractional order filter has also been carried out to investigate the deviation of the performance due to the parameter variation.

Repetitive Process Control Theory Applied to the Modeling and Control of Ladder Circuits

Repetitive processes propagate information in two separate directions, one of which is temporal and the other can be spatial. A repetitive process makes a series of sweeps, or passes, through a set of dynamics over this finite duration and when each is complete the process resets. Moreover, the output produced on the previous pass explicitly contributes to the dynamics produced on the next one. Hence they can also be viewed as a class of periodic systems. They also pose control problems that cannot be solved by standard systems control theory and design algorithms. This paper gives new results on the application of the repetitive process control theory to the analysis of ladder networks.

ＬＣ梯子形回路や単位素子で得られる固有振動

Voltage and current of electricity or electro-magnetic wave are presented by complex functions. Since product of voltage and current represents power, power is presented by complex function. Real part of power presents energy, and imaginary part of power presents reactive power. Eigen oscillation is caused by reactive power. It is well known that unit element of distributed constant circuit has eigen oscillation. LC ladder circuit also has eigen oscillation. This paper shows the condition of a cascade matrix of the circuit having eigen oscillation.

RLC Circuit Model for the Scattering of Light by Small Negative Refractive Index Spheres

We study the scattering properties of very small spheres made of a negative refractive index (NRI) using circuit network principles. The Lorenz-Mie theory is used to represent the transverse magnetic and transverse electric scattering coefficients based on resistor, inductor, and capacitor (RLC) ladder circuit models derived from continued fractions. The lumped elements are then analyzed and a comparison is made between these new elements and those expected for conventional positive refractive index spheres. This provides an alternative interpretation for the fact that the scattering efficiency Qsca for NRI spheres with size parameters x <;<; 1 does not always obey Rayleigh's formula Qsca ~ x4. The RLC circuits obtained here, besides being very simple, provide accurate physical insights into the problem of the scattering of light by NRI spheres, therefore serving as a new theoretical background for studying the scattering properties of negative refractive index metamaterials.

Parasitic-Element Compensation Based on Factorization Method for Microwave Inverse Class-F/Class-F Amplifiers

A novel parasitic-element compensation design method with a combination of factorization and coefficient comparison for microwave inverse class-F/class-F amplifiers is proposed. This novel method is applicable to all circuit topologies, including L-C parallel and series resonance circuits, and ladder circuits with arbitrary order of the higher harmonic frequencies. The validity of the proposed method has been checked with a fabricated 1.9 GHz inverse class-F GaN-HEMT power amplifier, considering harmonic frequencies up to the fourth order. A drain efficiency of 77% and power added efficiency of 70% were obtained at 1.88 GHz.

Noncontact Surface Resistivity Measurement Using a Cylindrical Surface Potential Detector With a Corona Charger

A noncontact surface resistivity tester was developed by improving the charge decay measurement. The tester has a corona charger and surface potential detectors in a cylindrical grounded body. The corona charger provides a surface charge on the test material, and the surface potential detectors measure the traveling motion of the surface charge. The traveling speed of the surface charge is dependent on the surface resistivity of the test material; therefore, the surface resistivity can be determined without contact to the material. An equivalent circuit with a 1-D ladder circuit was predicted, which includes the surface resistance of the material, the volume resistance of air, and the capacitance between the cylinder and the test material. From analysis of the equivalent circuit, the surface resistivity for an insulative surface was found to be a function of ρs/(ρvδ), where ρs is the surface resistivity of the test material, ρv is the volume resistivity of air, and δ is the gap between the test surface and the cylinder. For conductive and dissipative surfaces, the surface resistivity is dependent on e0ρs/δ, where e0 is the permittivity of air. The measurement concepts were experimentally verified using a needle-type corona charger, two induction probes, and a surface potential meter. The predicted surface resistivity measured using this method was consistent with the surface resistivity measured with a contact-type surface resistivity tester.

Modeling of Vibrating-Body Field-Effect Transistors Based on the Electromechanical Interactions Between the Gate and the Channel

A coupled analysis method for the mechanical and electrical systems of vibrating-body field-effect transistors (VB-FETs) is described. To accommodate energy transfer between the gate and the FET channel, we represent the FET with a resistance–capacitance ladder circuit and use the Lagrange function to derive motion equations. By solving the equations, we derive the typical electrical characteristics of VB-FETs, namely, the transconductance and the current gain. The results show that the current gain is obtained even above the cutoff frequency of the FET at the antiresonance frequency of the mechanical vibrator. These characteristics strongly depend on the device dimensions and operating conditions. This means that a coupled analysis is helpful for determining an appropriate design of VB-FETs.

Design of a re-entrant double-staggered ladder circuit for V-band coupled-cavity traveling-wave tubes

The re-entrant double-staggered ladder slow-wave structure is employed in a high-power V-band coupled-cavity traveling-wave tube. This structure has a wide bandwidth, a moderate interaction impedance, and excellent thermal dissipation properties, as well as easy fabrication. A well-matched waveguide coupler is proposed for the structure. Combining the design of attenuators, a full-scale three-dimensional circuit model for the V-band coupled-cavity traveling-wave tube is constructed. The electromagnetic characteristics and the beam—wave interaction of this structure are investigated. The beam current is set to be 100 mA, and the cathode voltage is tuned from 16.8 kV to 15.8 kV. The calculation results show that this tube can produce a saturated average output power over 100 W with an instantaneous bandwidth greater than 1.25 GHz in the frequency ranging from 58 GHz to 62 GHz. The corresponding gain and electronic efficiency can reach over 32 dB and 6.5%, respectively.

A new equivalent circuit model for on-chip spiral transformers in CMOS RFICs

A new compact model has been introduced to model on-chip spiral transformers. Unlike conventional models, which are often a compound of two spiral inductor models (i.e., the combination of two coupled Π or 2-Π sub-circuits), our new model only uses 12 elements to model the whole structure in the form of T topology. The new model is based on the physical meaning, and the process of model derivation is also presented. In addition, a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. In order to verify the model's validity and accuracy, we have compared the simulated and measured self-inductance, quality factor, coupling coefficient and insertion loss, and an excellent agreement has been found over a broad frequency range up to the resonant frequency.

Fault detection in resistive ladder network with minimal measurements

Testing of integrated circuits has now become a very important part of the semiconductor industry. Testing alone exceeds the cost of designing and manufacturing. So it is important to device new techniques to reduce the time and effort spent in testing [1]. The basic idea of the work done is to come up with a strategy to identify any fault in a resistive ladder network with minimal measurements, thereby reducing the testing time, efforts and cost [1]. Ideally the whole ladder circuit should act as a single segment and one or two measurements should detect the fault (location and type of fault). But since that is not possible we split up the big ladder network into segments which are as big as possible and at the same time giving good fault coverage. The ladder network was split into segments of different sizes. For each size scenario we analyzed the fault coverage. A detailed analysis for 2-step (4 resistors), 3-step (6 resistors) and 4-step (8 resistors) ladder networks were carried out and the results were found to be in favor of the 3-step ladder.

Direct extraction of equivalent circuit parameters for on-chip spiral transformers

This paper compares model differences of transformers measured in 4-port and 2-port configurations. Although 2-port configuration is more appropriate for measurement and application, it brings tremendous difficulties to the model's parameter extraction. In this paper, a physics-based equivalent circuit model and its corresponding direct extraction procedure are proposed for on-chip transformers. The extraction is based on the measurement of 2-port configuration instead of the 4-port type, and it can capture the model parameters without any optimization. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. Thus, this method can be transferred to the modeling of other passive devices, such as on-chip transmission lines, inductors, baluns, etc. In order to verify the procedure's efficiency and accuracy, an on-chip interleaved transformer in a 90 nm 1P9M CMOS process has been fabricated. We compare the modeled and measured self-inductance, the quality factor, mutual reactive and resistive coupling coefficients. Excellent agreement has been found over a broad frequency range.

Typical patterns of oscillations in three-phase circuit

Symmetrical three-phase circuits are fundamental models of power systems. Although the circuits have structural symmetry, asymmetric patterns of oscillations have been observed in real power systems. This paper describes an approach to understanding typical patterns of oscillations in the three-phase circuits using symmetry. In order to figure out oscillation patterns, we introduce a three LC ladder circuit which has a higher symmetry than the three-phase circuit. Using only the symmetries of the three LC ladder circuit, we classify periodic oscillations and construct a lattice of those modes. Further, extending the method to almost periodic oscillations, we decompose and characterize typical almost periodic oscillations by their symmetry. Finally, by observing a global phase space in the three LC ladder circuit, we confirm typical oscillations in the three-phase circuit.

Parasitic Compensation Design Technique for a C-Band GaN HEMT Class-F Amplifier

A class-F/inverse class-F load circuit design method that includes parasitic elements such as drain-source capacitance and bonding wire inductance has been developed. For the class-F load circuit design, a reactance function which has zeros at even harmonic frequencies and poles at odd harmonic frequencies is expanded to an -ladder circuit including parasitic elements through the use of the second Cauer canonical form. For the inverse class-F load circuit design, the zero points and the poles are exchanged. One stage of the -ladder circuit can be approximately replaced to a distributed circuit element for higher frequency operation. The proposed method allows parasitic compensation up to an arbitrary harmonic order by adding zeros and poles. Additionally, if distributed circuit elements are used, the method also compensates frequency dispersive characteristics of microstrip lines. According to the proposed method, a class-F amplifier using an AlGaN-GaN HEMT has been fabricated at 5.8 GHz. The fabricated class-F amplifier delivered high efficiency characteristics, with a maximum drain efficiency of 79.9%, a maximum power-added efficiency (PAE) of 71.4%, and an output power of up to 33.4 dBm at 5.86 GHz.

The Quantized Differential Comparator in Flash Analog to Digital Converter Design

This paper proposes a Flash Analog to Digital Convsrter design based on the use of a Quantized Differential Comparator. The formulation explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, thus eliminating the need for a passive resistor array for the purpose. This work is an attempt to extend the TIQ method, which uses systematic sizing of devices in a conventional CMOS inverter to accomplish the same. The formulation allows very small voltage comparison and complete elimination of resistor ladder circuit. The design has been carried out for the TSMC 0.18u technology at MOSIS.

The direct evidence of substrate potential propagation in a gate-grounded NMOS

In this study, the scheme of direct substrate potential measurement is used to explore the real-time substrate potential of the gate-grounded NMOS (GGNMOS). Through the parasitic capacitor between two pins of the packaged device, the coupled voltage can be transmitted to the substrate. It can be found that the substrate potential varies with location and pulse time evolution under transmission-line pulse (TLP) stress. Moreover, the substrate potential can propagate along the channel of the GGNMOS. Based on our experimental results, the substrate potential propagation can affect the turn-on of parasitic n–p–n bipolar in the GGNMOS. To simulate this dynamic behavior, the equivalent RC ladder circuit in the substrate combined with a delta function is proposed and the calculated results match the real-time Si data very well.

Analysis of Rail Potential and Stray Currents in a Direct-Current Transit System

The diode-grounded scheme for stray-current collection in some systems, such as the Taipei rapid transit systems (TRTS), has been constructed to gather the stray current leaking from the running rails and avoid corrosion damage to the system as well as the surrounding metallic objects. During operation of the TRTS, a high potential between the negative return bus and system earth bus at traction substations, referred to as rail potential, has been observed on the Blue line between BL13 and BL16. Since the Blue and Red-Green lines have their running rails and stray-current collector mats in junction at the G11 station, the TRTS suspects that the impedance bond at G11 is the cause of rail potential rise. This paper presents the results of field tests for studying whether the impedance bond at G11 of the tie line has an impact on rail potential and stray currents in TRTS. The results show the rail potential can be reduced by disconnecting the impedance bond at G11 of the tie line so that the negative return current of the Blue line cannot flow to the rails of the Red-Green Line, and vice-versa. In addition, rail potential and stray currents occurring at a station of the Blue line are numerically simulated by using a distributed two-layer ladder circuit model. The simulation results are compared with the field-test results and they are consistent with each other.

The direct evidence of substrate potential propagation in a gate-grounded NMOS

In this study, the scheme of direct substrate potential measurement is used to explore the real-time substrate potential of the gate-grounded NMOS (GGNMOS). Through the parasitic capacitor between two pins of the packaged device, the coupled voltage can be transmitted to the substrate. It can be found that the substrate potential varies with location and pulse time evolution under transmission-line pulse (TLP) stress. Moreover, the substrate potential can propagate along the channel of the GGNMOS. Based on our experimental results, the substrate potential propagation can affect the turn-on of parasitic n–p–n bipolar in the GGNMOS. To simulate this dynamic behavior, the equivalent RC ladder circuit in the substrate combined with a delta function is proposed and the calculated results match the real-time Si data very well.

Understanding the behaviour of infinite ladder circuits

Infinite ladder circuits are often encountered in undergraduate electrical engineering and physics curricula when dealing with series and parallel combination of impedances, as a part of filter design or wave propagation on transmission lines. The input impedance of such infinite ladder circuits is derived by assuming that the input impedance does not change when a new block of impedance is added. However, the impedance derived from this assumption may lead to incorrect conclusions if it is not treated carefully. Sometimes, in the literature, the input impedance behaviour of infinite ladder circuits is referred to as a paradox, leaving students and educators in doubt. This study intends to clarify this confusion and help to better comprehend the behaviour of the input impedance of infinite ladder circuits.