kV SiC PiN Diodes Research Articles

Tailoring the Charge Carrier Lifetime Distribution of 10 kV SiC PiN Diodes by Physical Simulations

In this paper, Shockley-Read-Hall (SRH) lifetime depth profiles in the drift layer of 10 kV SiC PiN diodes are calculated after MeV proton implantation. It is assumed that the carbon vacancy will be the domination trap for charge carrier recombination and the SRH lifetime is calculated with defect parameters from the literature and proton-induced defect distributions deduced from SRIM calculations. The lifetime profiles are imported to Sentaurus TCAD and static and dynamic simulations using tailored lifetime profiles are carried out to study the electrical effect of proton implantation parameters. The results are compared to measurements, specializing on optimization of the trade off between on-state and turn-off losses, represented by the forward voltage drop, VT, and reverse recovery charge, Qrr, respectively. Both the simulated and measured IV characteristics show that increasing proton dose, or energy, has the effect on increasing forward voltage drop and on-state losses, while simultaneously, the localized SRH lifetime drop decreases the plasma level, increases the speed of recombination and decreases reverse recovery charge. Finally, TCAD simulations with different combinations of proton energies and fluences are used to optimize the trade-off between static and dynamic performances. Reverse recovery charge and forward voltage drops of these groups of diodes are plotted together, showing that a medium energy which induces the most defects in the depletion region relatively close to the anode gives the best dynamic performances, with a minimum cost of static performance.

Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

6.5 kV SiC PiN diode with JTE and p+ rings termination was fabricated and characterized. The static and dynamic performance of SiC PiN diode were compared with that of SiC JBS diode and silicon diode, while switched in combination with a silicon IGBT. SiC PiN provides clear advantage while operating at higher current densities (above 100 A/cm2) and had lower leakage current. When switched together with a silicon IGBT, they contribute to losses similar to that of a SiC JBS diode.

10 kV Silicon Carbide PiN Diodes—From Design to Packaged Component Characterization

This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.

Local Lifetime Control in 4H-SiC by Proton Irradiation

The effect of local lifetime control by proton irradiation on the OCVD response of a 10 kV SiC PiN diode was investigated. Carrier lifetime was reduced locally by irradiation with 800 keV protons at fluences up to 1x1011 cm-2. Radiation defects were characterized by DLTS and C-V profiling; excess carrier dynamics were measured by the OCVD and analyzed using the calibrated device simulator ATLAS from Silvaco, Inc. Results show that proton implantation followed by low temperature annealing can be used for controllable local lifetime reduction in SiC devices. The dominant recombination centre is the Z1/2 defect, whose distribution can be set by irradiation energy and fluence. The local lifetime reduction, which improves diode recovery, can be monitored by OCVD response and simulated using the SRH model accounting for the Z1/2 defect.

Fabrication of 4H-SiC PiN diodes without bipolar degradation by improved device processes

We developed a simple technology for fabricating bipolar degradation-free 6.5 kV SiC PiN diodes on the basal plane dislocation (BPD)-free areas of commercially available 4H-SiC wafers. In order to suppress process-induced basal plane dislocation, we first investigated the causes of BPD generation during fabrication and then improved the processes. We found that no BPD was induced on a flat Si-face, but a large number of BPDs were concentrated in the mesa edge after high-dose Al ions were implanted [p++ ion implantation (I. I.)] at room temperature (RT) followed by activation annealing. Therefore, we examined new technologies in device processes including (I) long-term high-temperature oxidation after the mesa process to remove etching damage in the mesa edge and (II) reducing the Al dose (p+ I. I.) in the mesa edge to suppress BPD generation. We investigated the effect of the Al dose in the mesa edge on BPD generation and bipolar degradation. The results indicated that no BPD appeared when the dose was lower than 1 × 1015 atoms/cm2 and when long-term high-temperature oxidation was applied after the mesa process. As a result, we successfully fabricated 6.5 kV PiN diodes without bipolar degradation on BPD-free areas. Moreover, the diodes are very stable when applying 270 A/cm2 for over 100 h. Photoluminescence (PL) observation indicated that no BPD was generated during the improved fabrication processes. Besides, the Ir-Vr measurements showed that the breakdown voltage was over 8 kV at RT. The leakage currents are as low as 7.6 × 10−5 mA/cm2 (25 °C) and 6.3 × 10−4 mA/cm2 (150 °C) at 6.5 kV. Moreover, this result is applicable not only for PiN diodes but also for MOSFETs (body diode), IGBTs, thyristors, etc.

6.5 kV 4H-SiC PiN Diodes without Bipolar Degradation

We designed, fabricated and evaluated 6.5 kV SiC PiN diodes. In order to suppress process-induced basal plane dislocation (BPD) in SiC PiN diodes, we improved the fabrication processes. The Ir-Vr measurements showed that the breakdown voltage was over 9 kV at room temperature (25 °C). The leakage currents (Ileak) at 6.5 kV are as low as 5.9×10-6 mA/cm2 (25 °C) and 9.7×10-5 mA/cm2 (150 °C). The maximum recovery loss among our switching test results was 6.7 mJ at 150 °C, 60 A. Moreover, the diodes fabricated on BPD-free area are very stable during applying 20 A current for 8~1000 h. Photoluminescence (PL) observation and KOH etching indicated that no BPD generated during improved fabrication processes.

12.9 kV SiC PiN Diodes with Low On-State Drops and High Carrier Lifetimes

Sharp avalanche breakdown voltages of 12.9 kV are measured on PiN rectifiers fabricated on 100 µm thick, 3 x 1014 cm-3 doped n- epilayers grown on n+ 4H-SiC substrates. This equates to a record high 129 V/µm for a > 10 kV device. Optimized epilayer, device design and processing of the SiC PiN rectifiers result in a > 60% blocking yield at 10 kV, ultra-low on-state voltage drop and differential on-resistance of 3.75 V and 3.3 mΩ-cm2 at 100 A/cm2 respectively. Open circuit voltage decay (OCVD) measured carrier lifetimes in the range of 2-4 µs are obtained at room temperature, which increase to a record high 14 µs at 225 °C. Excellent stability of the forward bias characteristics within 10 mV is observed for a long-term forward biasing of the PiN rectifiers at 100 A/cm2. A PiN rectifier module consisting of five parallel large area 6.4 mm x 6.4 mm 10 kV PiN rectifiers is connected as a free-wheeling diode with a Si IGBT and 1100 V/100 A switching transients are recorded. Data on the current sharing capability of the PiN rectifiers is also presented.

Characterization of Packaged 6.5 kV SiC PiN-Diodes up to 300 °C

Silicon Carbide bipolar diodes offer unique ultrafast switching behavior for high voltage and high power applications [1]. But due to the small chip size it is required to parallel a lot of dice and therefore it is necessary to get detailed information about the electrical and thermal behavior of single diodes. For the characterization in the full current and voltage regime we have developed a molded leadframe package. The package was designed with a lateral contact geometry and a high creepage distance of 20 mm, which enable us to characterize these diodes for high voltage applications. Forward and reverse I-V characteristics and turn-off behavior under hard switching conditions up to 300 °C are reported. Additionally the forward voltage stability and power cycling tests are discussed.

An Experimental Study of High Voltage SiC PiN Diode Modules Designed for 6.5 KV / 1 KA

The paper describes first results of 6.5 kV SiC PiN diode modules which are designed as neutral point valves for medium-voltage power inverters rated for 1000 A. The power module consists of 4 AlN DCB substrates soldered on an AlSiC base plate. Each DCB is equipped with 20 SiC PiN diodes operating in parallel. The total active area of all 80 diode chips is 5.68 cm². At the rated current of 2 x 500A the forward voltage drops from 4.1 V at room temperature to 3.9 V at an averaged junction temperature of 125°C. The switching experiments show a very low reverse recovery charge of about 30 µC only. The conduction loss is comparable to the corresponding 6.5 kV silicon diode whereas the dynamic loss is marginal with respect to the forward conduction loss if the switching frequency is held below 10 kHz.

A Molded Package Optimized for High Voltage SiC-Devices

We present first results on power cycling of 6.5 kV SiC PiN-diodes mounted into a molded package. The geometry of this lateral package was designed to fulfill the specifications of the electrical isolation and the creepage distances in the high voltage region of 6.5 kV. To evaluate the suitability of this package we used high voltage SiC PiN-diodes. The diodes were soldered onto a copper lead frame, wire bonded and covered by molding compound. The packaged diodes were characterized by electrical measurements before and during a power cycling test with a temperature swing of 90 K. These results showed long term stable behavior of the I-V characteristics of the diodes as well as the suitability of the package for high temperature and high voltage application of SiC devices.

6.5 kV SiC PiN Diodes with Improved Forward Characteristics

The paper compares static and dynamic characteristics of 6.5 kV SiC PiN diodes fabricated with different p-emitters. The version with the thickest p-emitter (4 µm) showed the lowest forward voltage (3.4 V at 100 A/cm²) and the lowest (negative) temperature coefficient. Forward voltage DC stress tests revealed a stability within the measurement error of the test apparatus (<50 mV). The dynamic performance showed a soft recovery even at 4 kV. The reverse recovery charge Qrr is analyzed for different forward currents and junction temperatures. The dynamic losses of the SiC PiN diode are marginal with view to the application in industrial inverters.

Recent progress in 3.3 kV SiC diodes

The electrical performance of 3.3 kV SiC Schottky, JBS and PiN diodes are compared. In forward mode, the 25 mm 2 Schottky exhibits better performances than the 2.6 mm 2 JBS and PiN diodes. On the other hand, due its very large active area, the Schottky diode show a leakage current of 1 mA, which is 100× and 1000× higher than that of the JBS and PiN diodes, respectively. In switching mode, the Schottky and JBS diodes show similar reverse current peaks (2 A at 300 °C), whereas it is 5× higher for the PiN diode. Concerning the surge current capability, the three diodes present similar surge current capability (around 55 A) at 25 °C. At 225 °C, we have observed a 50% decrease in the surge current of the Schottky diode whereas it is almost the same for the PiN and JBS diodes.

Bevel Mesa Combined with Implanted Junction Termination Structure for 10 kV SiC PiN Diodes

A 10 kV 4H-SiC PiN diode with an improved junction termination structure has been fabricated. An improved bevel mesa structure, nearly vertical side-wall at the edge of pn junction and rounded corner at mesa bottom, has been formed by reactive ion etching (RIE). The junction termination extension (JTE) region has been optimized by device simulation, and simulated breakdown voltage has been compared with experimental results. The locations of electric field crowding and diode breakdown have been discussed.

SiC Power Devices – An Overview

ABSTRACTAn overview of SiC Power Devices is provided. Progress in 1200 V SiC Schottky diodes, 1200 V SiC BJTs, 10-20 kV SiC PiN diodes and 2 kV SiC Power MOSFETs will be described. SiC Schottky diodes have already been commercialized. The next step of inserting these diodes in Si IGBT modules is happening now. Emphasis is placed on the problems and issues at the SiC device/process interface which need to be urgently addressed such as the roughness created during the implant anneals, reliability of the gate oxide under positive and negative bias, low current gain of the BJTs, forward voltage instability in the pn junctions etc. Overcoming these issues in the near future will be critical to the successful commercialization of SiC devices.