Kogge Stone Adder Research Articles

Comparative study of 16‐order FIR filter design using different multiplication techniques

This study represents designing and implementation of a low power and high speed 16 order FIR filter. To optimise filter area, delay and power, different multiplication techniques such as Vedic multiplier, add and shift method and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Various adders such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder are analysed for optimum performance study for further use in various multiplication techniques along with barrel shifter. Secondly optimisation of filter area and delay is done by using add and shift method for multiplication, although it increases power dissipation of the filter. To reduce the complexity of filter, coefficients are represented in canonical signed digit representation as it is more efficient than traditional binary representation. The finite impulse-response (FIR) filter is designed in MATLAB using equiripple method and the same filter is synthesised on Xilinx Spartan 3E XC3S500E target field-programmable gate array device using Very High Speed Integrated Circuit Hardware Description Language (VHDL) subsequently the total on-chip power is calculated in Vivado2014.4. The comparison of simulation results of all the filters show that FIR filter with WT multiplier is the best optimised filter.

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.

Register-Less NULL Convention Logic

NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge–Stone adder can reduce power dissipation by 56.4%–72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs

Adders are the most fundamental arithmetic units, and often on the timing critical paths of microprocessors. Among various adder configurations, parallel prefix adders provide the best performance vs. power/area trade-off, especially for higher bit-widths. With aggressive technology scaling, the performance of a parallel prefix adder, in addition to the dependence on the logic-level, is determined by wire-length and congestion which can be mitigated by adjusting fan-out. This paper proposes a polynomial-time algorithm to synthesize ${n}$ bit parallel prefix adders targeting the minimization of the size of the prefix graph with ${\log _{2} n}$ logic level and any arbitrary fan-out restriction. A structure aware prefix node cloning is then applied to the resultant prefix adder solutions to further optimize the size of the prefix graphs. The design space exploration by our approach provides a set of pareto-optimal solutions for delay vs. power trade-off, and these pareto-optimal solutions can be used in high-performance designs instead of picking from a fixed library (Kogge–Stone, Sklansky, etc.). Experimental results demonstrate that our approach: 1) excels highly competitive industry standard Synopsys design compiler adder, regular adders such as Sklansky adder and Kogge–Stone adder, and a highly run-time/memory intensive recent algorithm in 32 nm technology node and 2) improves performance/area over even 64 bit custom designed adders targeting 22 nm technology library and implemented in an industrial high-performance design.

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder

Objective: VLSI integer adders are critical elements in general purposed DSP and DSPA processors. These used in design of ALU, floating point arithmetic data paths and address generation units. Parallel prefix adders rely on simple cell design. Modern FPGAs utilize fast carry chain for optimization ripple carry adder. Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper. Prefix adder with reversible logic gates utilizing 16 bit kogge stone adder have been design using PERES logic. Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes. The adder structure has minimum logic depth and binary tree structure with minimum fan-out. From the simulate results this is formed that computational path net delay for 16 X16 bit prefix adder using reversible logic is 20.828 ns with Kogge Stone Adder is reading to 17.247ns. Novelty/Improvement: The multiple based on 16 bit Kogge Stone Adder is formed to be less efficient than the case of reversible adder in term of delay and power analysis.

High Speed 32-bit Vedic Multiplier for DSP Applications

signal processing typically requires large number of mathematical operations to be performed repeatedly on the samples of data with less delay and power consumption. Multiplication is the fundamental arithmetic operation and determines the overall execution time of the processor. In this paper two high speed 32-bit Vedic multipliers are designed based on Urdhva-Triyakhbhyam sutra. Addition of partial products of proposed multipliers is done using Kogge stone adder and ripple carry adder respectively. Proposed multiplier-1 and proposed multiplier-2 were compared with the one with the highest speed and a reduction of 77% and 65.37% is achieved respectively. The coding is done using Verilog HDL and synthesized using cadence tool.

An Efficient Processing by using Kogge-Stone High Speed Addition Technique

In this Technical era the high speed and low area of VLSI chip are veryvery essential factors. Day by day number of transistors and other active and passive elements are drastically growing on VLSI chip. All the processors of the devices adders and multipliers are played an important role. Adder is a striking element for the designing of fast multiplier. Ultimately here need a fast adder for high bit addition. In this paper, proposed Kogge-Stone adders are used for binary addition to reduce the size and increase the efficiency or processors speed. Proposing Kogge stone adder provides less components, less path delay and better speed compare to other existing Kogge Stone adder and other adders. Here we are comparing the Kogge Stone adders of different-different word size from other adders. The design and experiment can be done by the aid of Xilinx 14.2i Spartan 3E device family. General Terms Ripple carry and Kogge Stone adder, analysis and simulation software tool, Xilinx 14.2i Spartan 3E device.

Adaptive power gating of 32-bit Kogge Stone adder

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.

Static Differential NCL Gates: Toward Low Power

This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. It shows that albeit the extra transistors adding cost in area, they enable solid savings in dynamic and static power and improve transition delays. Electrical simulation results for a Kogge-Stone adder case study led to savings of 67.3% in dynamic power, 61.9% in static power, 67.2% in energy per operation, and 8.9% in forward propagation delay, when compared with a state-of-the-art differential topology.

Design of a High Speed Adder

In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler. Index Terms Adder, Carry Select Adder, Kogge Stone Adder, Verilog HDL. ——————————  ——————————

Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis

This paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed circuits show an energy efficient agreement with Spectre simulations using BSIM3v3 and BSIM4 models for 90nm CMOS technology at 0.4V supply voltage. The adder implementation outperforms its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional adders operated in the sub-threshold region.

Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep

null convention logic (NCL) is a promising design paradigm for constructing asynchronous delay-insensitive circuits. This brief presents two novel NCL pipeline structures, called fine-grain power gating NCL with early sleep (FPG-NCL-ES) and fine-grain power gating NCL with early sleep and optimization (FPG-NCL-ES-OPT), which employ both fine-grain power gating and early sleep to achieve lower power consumption. With fine-grain power gating, a logic block in FPG-NCL-ES becomes active only when performing useful work and is power gated to reduce leakage power when inactive. Moreover, with the early sleep mechanism, the multithreshold CMOS (MTCMOS) threshold gates in a pipeline stage can enter the sleep mode early once the data output of this stage has been received by the downstream pipeline stage, without waiting for the next null wavefront to arrive at this stage. Thus, the MTCMOS threshold gates in the FPG-NCL-ES pipeline have a higher probability of staying in the sleep mode than those in the traditional power-gated NCL pipeline. A modified asymmetric C-element is proposed to replace the traditional C-element for supporting early sleep. The FPG-NCL-ES-OPT pipeline employs a circuit simplification to further reduce silicon area and power consumption. Simulation results show that, compared with the traditional NCL counterpart, the FPG-NCL-ES-OPT implementation of the Kogge–Stone adder can achieve a higher maximum sustainable throughput rate, lower power consumption, and lower hardware cost.

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

In this paper, a metastability immune warning flip-flop (FF) is proposed, which consists of an edge detector, a warning window generator, and a warning detector along with a traditional FF. The delayed data are monitored during the warning window to flag a warning signal before the data enter the erroneous zone. In this scheme, the warning window is independent of input clock frequency and hence is suitable for frequency scaling application. A 16-bit Kogge-stone adder is implemented in 65-nm technology, which uses warning FF for dynamic voltage and frequency scaling (DVFS). The warning FF-based DVFS allows elimination of safety margins and operates till the point of first warning of the adder without any erroneous results. The experiments were conducted with different supply voltages, phase-shifted clocks, and process conditions. The circuit is helpful to determine when to stop further reduction in supply voltage by producing the warning signal with predefined timing slacks in DVFS application. The test chip results demonstrate that the proposed circuit can track the critical path delay of 2.4-7.5 ns at warning voltage of 1.15-0.72 V, respectively. The measured results from 10 different chips show the effectiveness of the proposed concept across process variation.

A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling

Drastic yield reduction at sub/nearthreshold voltage domains, caused by the severe process, voltage, and temperature (PVT) variations in this region, is challenging characteristic of recent nanometre sensory chips. Using a variation sensitive and ultra-low-power design, this paper proposes a novel technique capable of sensing and responding to PVT variations by providing an appropriate forward body bias (FBB) so that the delay variations and timing yield of whole system as well as energy-delay product (EDP) are improved. Theoretical analysis for the error probability, confirmed by post-layout HSPICE simulations for an 8-bit Kogge–Stone adder and also two large Fast Fourier Transform (FFT) processors, shows considerable improvements in severe PVT variations and extreme voltage scaling. For this adder, for example, the proposed technique can reduce error rate from 50% to 1% at 0.4V. In another implementation, in average ∼7× delay variation and ∼4× EDP improvement is gained after this technique is applied to an iterative 1024pt, radix 4, complex FFT while working in sub/nearthreshold voltage region of 0.3V–0.6V. Also, pipelined version of the FFT consumed only 412pJ/FFT at 0.4V while processing 125K FFT/sec.

MOS Current Mode Logic Near Threshold Circuits

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

Design of RSFQ wave pipelined Kogge–Stone Adder and developing custom compound gates

Since the invention of computers, the calculation of arithmetic and logic operations using digital circuits has been one of the leading problems in processor designs. The challenge has been to compute more operations with less clock cycles by using additional specific logic circuits. One of the most fundamental processes is addition; in which the carry bit should be transferred from the least significant bit to the most significant one. A wide range of digital circuit designs have been sustained for specialized faster addition operation. One of these adder algorithms is Kogge Stone Adder which does faster calculation with fewer levels and minimum fan-out compared to today’s adders despite the only disadvantage of having an excessive amount of wiring.In this study, a custom Rapid Single Flux Quantum (RSFQ) based, wave pipelined, Kogge Stone Adder is proposed to be used later in an Arithmetic Logic Unit (ALU). Two different design methodologies have been considered. In the first approach, we used standard logic gates for the whole adder design. In the second approach, utilization to compound gate design with adjustments over component parameters is done by using Particle Swarm Optimization and Statistical Timing Analysis Tools, to increase both efficiency and bias margin.

Improved Fault Tolerant Sparse KOGGE Stone ADDER

A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry tree but no error detection is possible. This proposed design is based on fault tolerant adder [1] that uses Sparse kogge-stone adder that is capable of both fault detection and correction. Fault tolerance is achieved by using two additional ripple carry adders that form the basis of triple mode redundancy adder. Triple mode redundancy is one of the most common methods used to create fault tolerant designs in both ASIC and FPGA implementations. The latency will be increased because of the voter in the circuit’s critical path. More advanced fault tolerant methods exist including roving and graceful degradation approaches. Allowing fault tolerance to operate at different levels of

A highly sensitive and ultra low‐power forward body biasing circuit to overcome severe process, voltage and temperature variations and extreme voltage scaling

SummaryDynamic voltage scaling is one of the most popular methods used to reduce energy consumption in today's digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation‐sensitive and ultra low‐power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy‐delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post‐layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8‐bit pipelined Kogge–Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3 V and temperature changes of −15 to 75 °C, the proposed technique brought about a seven times less delay variation, whereas energy‐delay product improved by 23% compared with a zero body biased adder. Copyright © 2013 John Wiley & Sons, Ltd.

16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder

In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8%/-10.7%.

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

We propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predict the parity of the result. The adder uses parity-based error detection and it has high compatibility with systems that have parity-based error detection. We can implement various fault-secure parallel prefix adders such as Sklansky adder, Brent-Kung adder. Han-Carlson adder, and Kogge-Stone adder. The area overhead of the proposed adder is about 15% lower than that of a previously proposed adder that compares all the carry bits.