kHz Signal Bandwidth Research Articles

A 1.2 V, 92 dB Dynamic-Range Delta-Sigma Modulator Based on an Output Swing-Enhanced Gain-Boost Inverter

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient integrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power consumption is 210 μ W, corresponding to a Schreier figure-of-merit value of 171.1 dB.

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

DAC mismatch is a major challenge for high-resolution ADCs. This paper proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm and consumes 0.656 μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

Experimental demonstration of spatial division multiplexing multiple-input/multiple-output underwater acoustic communication using a time-reversal method at the depth of the continental shelf: a consideration of optimization of signal length and number of transmission channels

In this paper, the performance of the adaptive passive time-reversal method is investigated for an at-sea experiment of multiple-input/multiple-output underwater acoustic communication over a range of 13.5 km. The experiment was conducted at a depth of 200 m utilizing up to five transmitters with 4–8.5 kHz signal bandwidth for spatial division multiplexing. It was confirmed that the performance depends on the delay time from the timing of the channel response estimation to the communication signal reception, and the optimal signal length and the number of transmission channels can be determined according to the required bit error rate (BER) for the system. As a result, using the optimal signal length and a number of transmission channels, effective data rates of 30.21 and 37.53 kbps are achieved with BER ranges of less than 0.1% and 1%, respectively, with more than 90% of received communication signal packets.

9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids

In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier’s source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator’s effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively.

Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC

In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimize power consumption. To further improve its energy efficiency, a gain enhancement current mirror OTA is designed and the SAR ADC adopts upper plate sampling technique. The layout of zoom ADC occupies 0.856 mm2 in 65 nm techniques. It achieves 109.2 dB SNDR, 17.84 bits ENOB at 1 kHz signal bandwidth and consumes only 0.233 mW.

Integrated three-dimensional Hall switch sensor based on independent optimized Hall devices

This paper presents an integrated 3D Hall switch sensor with a 100 kHz signal bandwidth, which can detect three-dimensional (3D) magnetic field and output digital signals. 3D magnetic field detection relies on the integration of the horizontal Hall devices (HHD) and vertical Hall devices (VHD), and usually requires the performance of HHD and VHD to match each other. Therefore, an independent optimization method is applied to 3D Hall sensor to realize the matching between HHD and VHD. This method allows the doping concentration and doping profiles of VHD can be designed different from HHD. The simulation results show that the optimized HHD can achieve a voltage sensitivity SV of about 20mV/VT and a residual offset of 20 μV at a 3.3 V supply voltage, while VHD are optimized independently for SV up to 20mV/VT, and the residual offset is less than 100 μV after applying offset cancellation technology. In addition, in order to reduce the power consumption and area of the Hall sensor, the Hall signal processing circuit adopts the time-division multiplexing method to realize the detection of the 3D magnetic field in one working period. During the working period, the circuit uses logic control timing circuit to realize wake-up and sleep mode, which further effectively reduces the overall power consumption of the sensor. The Hall sensor chip has been fabricated in 0.18 μm CMOS technology with an area of 1.46 mm2. The measured results show the power consumption of the chip in the Z-axis direction is about 11.88 mW in the wake-up mode and only 49 μW in the sleep mode, at a 3.3 V supply voltage.

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power using a 1.6 V power supply.

A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback

This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer's input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a 0.11 μm CMOS process using four metal layers with an active die area of 0.165mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves a dynamic range (DR) of 96.3 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming 62.43 μW from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171dB.

Simultaneous thermometry and magnetometry using a fiber-coupled quantum diamond sensor

Energy conservation and battery life extension are key challenges for the next-generation hybrid electric vehicles. In particular, the temperature and electric currents in a storage battery need to be monitored simultaneously with ∼1 kHz signal bandwidth for optimum battery usage. Here we introduce a centimeter-scale portable quantum sensor head, consisting of a diamond substrate hosting an ensemble of nitrogen-vacancy (NV) color centers with a density of ∼3 × 1017 cm−3. One diamond surface is attached to a multi-mode fiber for simultaneous optical excitation and readout of the NV centers, while the other diamond surface is attached to a coplanar microwave guide for NV spin ground-state mixing. Signal bandwidth of 1 kHz was realized through time-domain multiplexing of the two-tone microwave frequency modulation at 20 kHz. Two microwave frequencies were locked to the two resonance points that were determined from the optically detected magnetic resonance spectrum. From the mean and the difference of the deviation from the two locked frequencies, the temperature and magnetic field were obtained simultaneously and independently, with sensitivities of 3.5 nT/Hz1/2 and 1.3 mK/Hz1/2, respectively. We also showed that our sensor reached a minimum detectable magnetic field of 5 pT by accumulating signals for over 10 000 s.

100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

Efficient CTDSM based on GM‐C quantiser and improved dynamic element matching

In this study, a continuous-time delta-sigma modulator (CTDSM) is developed using a Gm-C based noise-shaping quantiser (Gm-C-NSQ) with an improved dynamic element matching (i-DEM) algorithm. Here, a Gm-C integrator is used to develop NSQ, since it increases the effectiveness of the proposed modulator in terms of power consumption and die area. This Gm-C-NSQ uses only three dynamic latches to provide efficient quantisation level and to increase the order of noise shaping. Moreover, an i-DEM algorithm is utilised to reduce the non-linearities of the quantiser and mismatching error of the digital-to-analogue converters presented in the feedback structure of the modulator. Here, an 180 nm CMOS technology is used to design the proposed modulator and it functions at 2.6 MHz sampling frequency. Simulation results show that the proposed modulator can achieve a peak spurious-free dynamic range (SFDR) of 93.67 dB and a peak signal-to-noise ratio of 87.38 dB for 20 kHz signal bandwidth. Furthermore, the proposed modulator consumes 0.0863 mW power when 1.2 V supply voltage is applied.

Design of A 1-V 3rd-order 1-bit Σ-Δ modulator with inverter-based static–dynamic hybrid structure amplifiers

A 1-V 3rd-order 1-bit discrete time (DT) Σ-Δ modulator is designed and implemented in a 40-nm CMOS technology. With the input feed forward coefficient optimized, the output swings of the integrators are minimized. The bootstrapped switches are utilized at the input of the modulator to improve the linearity of the sampled signal. In order to reduce the power consumption in low voltage environment, the inverter-based static–dynamic hybrid structure amplifier is proposed and a dynamic comparator is employed. The designed modulator achieves 89.8 dB maximum SNR and 84.1 dB maximum SNDR over a 100 kHz signal bandwidth with a sampling frequency of 25.6 MHz, and the dynamic range (DR) is 86.7 dB. The proposed modulator shows competitive figure of merits (FOMs) compared with other near-1V-supply hundred-kHz-BW modulators.

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

A silicon Hall sensor SoC for current sensors

In this paper we present a System on Chip (SoC) that implements a Hall Effect Sensor along with its readout circuits and calibration support. The sensor is designed for use in Hall effect based current sensors. The SoC was implemented in 0.18u CMOS technology and integrates Hall sense elements, preamplifiers as well as a delta sigma ADC, a DAC and a digital calibration. The SoC achieves 11 V/T gain and 0.76% RMS accuracy over a range of ±300 mT and 30 kHz signal bandwidth. The SoC integrates a digital correction unit that implements a polynomial computation algorithm for calibrating out the current sensor’s magnetic core induced nonlinearities. Offset temperature drift of the sensor is 6.81μT per degrees over −40 °C to 85 °C range. A current sensor is built using the SoC. It can measure currents from −10 A to 10 A and achieve 1.67% RMS measurement accuracy.

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.

A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers

This brief presents a 0.6 V third-order continuous-time sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an on-chip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and temperature variations. Also, a negative resistance is used at the output of the amplifier to enhance dc gain. To increase power efficiency, a single-amplifier resonator is used in the loop filter. To enable this implementation a compensation technique to mitigate the effects of amplifier’s finite dc gain in the resonator transfer function is presented. The proposed CT-SDM was fabricated in a 130-nm CMOS process with an active area of 0.232 $\mathrm {mm^{2}}$ . The modulator achieves a 74.2 dB DR and peak SNDR/SNR of 59.43/69.04 dB for a 100 kHz signal bandwidth while consuming 89.50 $\mathrm {\boldsymbol \mu W}$ from a 0.6-V power supply.

A 1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mW from a 1.0 V power supply. The prototype chip occupies 0.16 ㎟ using a 0.13 mm CMOS technology.

A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path

This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.