kHz Offset Frequency Research Articles

개선된 바랙터 결합 선로를 이용한 Ku-Band 헤어핀 발진기 설계

본 논문에서는 개선된 바랙터 결합 선로를 제안하고, 이 구조를 사용한 주파수 합성기를 설계 제작하였다. 제안된 결합 선로는 기존 구조에 추가적인 <TEX>$\lambda$</TEX>/4 전송 선로를 이용하여 바랙터에서 반사되는 잡음신호를 제거하는 구조이다. 제작한 주파수 합성기는 Ku-band 대역에서 헤어핀 공진기를 사용하였으며, PLL을 사용하여 주파수를 고정하였다. 제안된 구조로 제작한 헤어핀 발진기의 경우, 38 MHz의 주파수 조정 범위와 100 kHz offset에서 -97 dBc/Hz의 위상 잡음을 나타내었다. 이러한 측정 결과는 제작한 기존 구조의 바랙터 결합 선로를 가지는 헤어핀 발진기보다 30 MHz 개선된 주파수 조정 범위와 8 dB 개선된 위상 잡음 특성을 가지는 것으로 확인되었다. In this paper, we propose a new varactor coupled line structure and design the VCO using the proposed structure. The proposed coupled line structure removes the reflected signals from the varactor diode using an added <TEX>$\lambda$</TEX>/4 transmission line. The frequency synthesizers are designed using the PLL technique at Ku-band. The synthesizer using the proposed coupled structure has 38 MHz frequency tuning range and -97 dBc/Hz phase noise characteristic at 100 KHz offset frequency. The measured results show improved tuning range as well as the improved phase noise characteristics compared to the conventional designs.

Medium power C‐band array amplifier featured ultra low residual phase noise

AbstractThis article deals with a design and performance evaluation of a medium power C‐band array amplifier based on SiGe hetero‐junction bipolar transistors (HBT). The proposed power amplifier (PA) contains four identical HBT stages coupled by the means of compact power splitting/summing microstrip networks. The designed PA exhibits a very low phase noise level of −165 dBc/Hz at 1 kHz offset frequency, and it is distinguished by a high output power having P1dB = +26 dBm and high power added efficiency approaching to 40%. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 292–295, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24896

A Design and Measurement of a Reference Signal Generator for a Radar System

This paper discusses the design and fabrication of a reference signal generator for a naval radar system, including the vibration environment test. The transmit signals of the S-band radar system are synthesized by the reference signal and the phase noise must lower than - 130 dBc/Hz at a 10 kHz offset frequency. To achieve this specification, the phase noise of the reference signal needs to be less than -165 dBc/Hz at a 10 kHz offset. For achieving very low phase noise performance by the reference signal generator, the phase locked loop technique is applied with a 10 Hz loop bandwidth. Also, this reference signal generator has <TEX>${\pm}0.35\;ppb$</TEX> short-term stability to minimize instant phase errors and high vibration sensitivity against a ship's shaking, unbalanced rotating of antennas and so on.

개루프 방법에 의한 확장된 전기적주파수조정범위를 갖는 유전체공진기발진기의 설계 및 제작

In this paper, we presented a Vt-DRO with a wide electrical frequency tuning range, using open-loop gain method. The Vt-DRO was composed of 3-stages, resonator, amplifier and phase shifter. In order to satisfy an oscillation condition, we determined magnitude and phase of each stage. The measured S-parameter of cascaded 3-stages shows open-loop oscillation condition. Also, using measured open loop group delay, we derived the relation for electrical frequency tuning range. The Vt-DRO was implemented by connecting the input and the output of the designed open-loop and resulted in closed-loop. As a results, tuning-range of Vt-DRO is 82 MHz, which is close to the predicted results for tuning voltage 010 V and shows linear frequency tuning at the center frequency of 5.3 GHz. The phase noise is -104 1 dBc/Hz at 100 kHz offset frequency and power is 5.861 dBm respectively.

Method of power recycling in CoAxial Mach-Zehnder interferometers for low noise measurements

We present the first experimental study of a new type of power recycling microwave interferometer designed for low noise measurements. This system enhances sensitivity to phase fluctuations in a device under test, independent of input power levels. The single sideband thermal white phase noise floor of the system has been lowered by 8 dB (reaching -185 dBc/Hz at 1 kHz offset frequency) at relatively low power levels (13 dBm).

Improved Bias Stability of the Resonant Tunneling Diode Pair Oscillators Integrated on an AlN Ceramic Substrate

Resonant tunneling diode (RTD) pair oscillators were fabricated on an AlN ceramic substrate employing a novel integration process based on an assembly of small device blocks. By using this process, chip capacitors were mounted close to the oscillator without large parasitic inductance. This can relax the severe condition for bias stability. Stable oscillations were observed in the fabricated circuits at 35–50 GHz. A good single sideband phase noise of -100 dBc/Hz at a 100 kHz offset frequency was also observed for the fabricated circuit.

고온초전도체와 유전체 삽입 공동 공진기를 이용한 발진기의 위상잡음 개선에 관한 연구

In this paper, an oscillator using dielectric-rod loaded cavity resonators with HTS(High Temperature Superconductor) end-plates was presented. It was operated at X-band. A two port cavity resonator was incorporated into a basic feedback loop oscillator configuration. A rutile loaded cavity resonator with HTS thin film end-plates was used to provide the quality factor between <TEX>$10^4$</TEX> and <TEX>$10^6$</TEX>. A parallel feedback oscillator was constructed with a dielectric loaded cavity resonator, an amplifier, and a directional coupler. At 300 K, the experimental results showed the phase noise of -108 dBc/Hz at a 100 kHz offset frequency. At 26 K, the results was -118.8 dBc/Hz at same offset frequency.

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With $-$75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.

A 3-band CMOS DTV Tuner IC for DVB-C Receiver

A 3-band DTV tuner IC for DVB-C is designed in 0.25-mum CMOS process in this paper. The IC integrates not only mixer, PLL, but also an IF variable-gain amplifier. The mixer is based on Gilbert cell, and a transconductance linearization scheme is adopted to realize the highly linear, wide-range CMOS IF variable-gain amplifier with exponential gain control. A novel analog automatic amplitude controller based on charge-pump is proposed to stabilize performance across the 900-MHz tuning range without degrading the phase noise of VCO. An improved dual-module prescaler has wideband high input sensitivity. With 3.3 V supply voltage, the measurements show that the mixer has voltage gain of 35 dB, the variable-gain amplifier provides continuous gain control range of 40dB, a C/IM3 of 61.2 dBc at 1-Vpeak-to-peak output, and the phase noise is below -82dBc/Hz at the 10 kHz offset frequency within the whole tuning range. The STB based on the designed IC has received cable DTV clearly.

소형화된 Ka-대역 주파수 합성기 모듈 설계 및 제작

In this paper, we designed and fabricated a Ka-band synthesizer module. In addition, the systematic layout procedure and the test procedure were presented for the construction of compact synthesizer. To implement the Ka-band synthesizer, X-band VCO is employed as VCO and its frequency was multiplied by 3 with frequency tripler. The fabricated frequency synthesizer shows a frequency tuning range of 500 MHz, output power of about 14 dBm, and a phase noise of -96.17 dBc/Hz at the 100 kHz offset frequency.

Push‐push voltage controlled dielectric resonator oscillator using a LTCC technology

AbstractA push–push voltage‐controlled dielectric resonator oscillator (VCDRO) with a modified frequency tuning structure is investigated. The push–push VCDRO designed at 16 GHz is manufactured using a low temperature cofired ceramic (LTCC) technology to reduce the circuit size. The frequency tuning structure is embedded in a layer of A6 substrate by an advantage of LTCC process. Experimental results show that the fundamental frequency suppression is above 30 dBc, and a phase noise of push–push VCDRO presents a good performance of −103 dBc/Hz at 100 kHz offset frequency from carrier. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1824–1827, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22619

공진기의 결합 특성을 개선한 Push-Push 발진기 설계

This paper introduces a new type push-push harmonic dielectric resonator oscillator. Proposed oscillators are utilized by HDRO(Harmonic Dielectric Resonator Oscillator) which are combined in push-push structure. As a result, fundamental signal suppression ratio and output power of harmonic signal has been improved. The increase of phase noise is compensated by improving coupling characteristic between resonator and parallel microstrip line. The proposed push-push HDRO shows the output power of 9.32 dBm, the fundamental signal suppression of -47.2 dBc and phase noise of -99.86 dBc at 100 kHz offset frequency and 18.7 GHz center frequency.

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both fT and fmax. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mVpp. The extracted 40 GHz clock signal shows a phase noise as low as -98 dBc/Hz at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of -4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies

A fully integrated fractional-N frequency synthesizer with a wideband VCO and a 3-bit 4th order Σ–Δ modulator for GSM/GPRS/EDGE applications

Abstract A fully integrated fractional-N frequency synthesizer (FNFS) in 0.5 μm SiGe BiCMOS technology is implemented. To cover wideband frequency operation, a switched capacitor bank LC tank VCO and an Adaptive Frequency Calibration (AFC) technique are used. A 3-bit 4th order Σ–Δ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz, and agile switching time. The experimental results show −80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and −129 dBc/Hz out-of-band phase noise at 400 kHz-offset frequency. The fractional spurs are less than −70 dBc/Hz at 300 kHz offset frequency and the reference spur is −75 dBc/Hz. The lock time is less than 150 μs. The proposed synthesizer consumes 19.5 mA from a single 2.8 V supply voltage and meets the requirements of GSM/GPRS/EDGE applications.

Oscillator Design and Fabrication using a Miniatured Hairpin Resonator

In this papers, an S-band oscillator of the low phase noise property using a miniaturized micro-strip hairpin shaped ring resonator is presented The substrate has a dielectric constant <TEX>$\epsilon_\gamma$</TEX>＝3.5, a thickness h＝0.508 mm, and loss tangent <TEX>$tan\delta$</TEX>＝0.002. A designed and fabricated oscillator shows low phase noise performance of 99. 71 dBc/Hz at 100 KHz offset frequency and of output power 19.584 dBm at center frequency 2.450 GHz. This circuit was fabricated with hybrid technique, but can be fully compatible with the MMIC due to its entirely planar structure.

All-optical harmonic frequency upconversion of radio over fibre signal using cross-phase modulation in semiconductor optical amplifier

All-optical harmonic frequency upconversion into the microwave frequency band for a WDM-based radio over fibre application is experimentally demonstrated by using a cross-phase modulation effect in a semiconductor optical amplifier. Maximum frequency conversion efficiencies from 2.5 GHz (fIF) to 12.5 GHz (fLO±fIF) and 22.5 GHz (2fLO±fIF) are 13.2 dB and 3.1 dB, respectively. The conversion efficiency to 2fLO±fIF is larger than unity for the IF signal wavelength range between 1547.22 and 1556 nm. The phase noise of the upconverted signal at 22.5 GHz is −80.0 dBc/Hz with 1 kHz offset frequency, which is limited by that of the LO source.

마이크로파 레이더 센서 응용을 위한 발진기 설계 및 제작

Recently, sensors which use the infrared light, supersonic waves, and electromagnetic waves have been used for many applications to detect information of the object. For these sensors, the accompanying system which utilizes the sensor should be systematically developed. In this paper, a general microwave radar sensor system is briefly described, and then basic applications of a CW doppler radar sensor system are introduced. For the CW doppler radar sensor applications, a highly-stable, low-cost Dielectric Resonator Oscillator (DRO) has also been designed and implemented, which can be used for commercial microwave sensor systems. The implemented DRO has output power of +5.33 dBm at 12.67 GHz and phase noise of -108.5 dBc/Hz at the 100 kHz offset frequency.

Optical control of period doubling in a gain-switched Fabry–Perot laser diode and its application in all-optical clock division

Optical injection is shown to be an effective means to suppress or to enhance period doubling of a gain-switched laser diode. The role that the injection plays depends on whether the laser resonance frequency is larger or smaller than half the modulation frequency. Reversible control of period doubling has been demonstrated experimentally using a modulated injection source. An injection power as low as 0.03 mW has been used to control the output pulse repetition frequency of the slave laser. The response time is measured to be shorter than 100 ps. The phenomenon has been applied successfully for use in all-optical clock frequency division. Replacing the electrical modulation with an input clock signal at 19.6 GHz, a frequency-halved output clock with a remarkable low-level phase noise (−87.7 dBc/Hz at 10 kHz offset frequency) has been obtained. The change in the phase noise level is observed to be smaller than 1 dB over a frequency detuning range of 400 MHz.

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.

A 10.7-MHz IF-to-baseband /spl Sigma//spl Delta/ A/D conversion system for AM/FM radio receivers

/spl Sigma//spl Delta/ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time /spl Sigma//spl Delta/ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm/sup 2/ in 0.25-/spl mu/m standard digital CMOS. The /spl Sigma//spl Delta/ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW.