Key Expansion Research Articles

Generation Initial Key of the AES Algorithm based on Randomized and Chaotic System

information security is a critical concern and a top priority for many communications networks. Cryptography is a suitable method of data security that can be used to maintain the secrecy and authenticity of information and can improve the privacy aspect of the data. The AES algorithm is one of the most important encryption algorithms and the best in protecting data. In this paper, a comparison was made between two different methods for the generation initial key of the key expansion of the AES-192 algorithm, in the first method, the initial key generated by the user (chose a random key by the user), and in the second method, the initial key generated by the chaotic system (which used the logistic function to generate the numbers chaotically). After testing the two methods, the second method that used a chaotic system is faster and more secure than the first method. Also, the encryption and decryption operations using the key generated by the chaotic system were faster when applying it to various sizes of text files and the plaintext is difficult to discover from the ciphertext. When comparing the proposed method to earlier experiments, it is both quicker and messier than earlier encryption techniques.

FPGA Implementation of Enhanced Throughput Design of AES Architecture using Nikhilam Sutra

The exponential growth of the internet and contemporary communications users have established safety as a fundamental design feature for encrypted transmission. The Enhanced Cryptography Standard is perhaps the most widely used cryptography information security algorithm standard that has been authorized by NIST. This paper proposes a high-throughput design for the AES Algorithm with huge key sizes. AES would be a block cipher that ensures data security by using key lengths of 128,192 and 256-bits. The design concept focuses on a 256-bit key size classification algorithm since a big key size is required to ensure excellent security. Additionally, simultaneous key expansion & encryption/decryption processes would be pipelined to maximize speed. Parallelization of a key expansion module's sub-processes would be used to reduce the critical chain latency. The S-box comprising sub-byte & inverse sub-byte operations has been developed with compound field arithmetic operations to reduce time and area further. The work Increased throughput by 50%, area reduced by 34.32 %, and latency by 20% compared to the old approach with modified nikhilam sutra. Additionally, integrated AES encryption/decryption is planned and implemented on the FPGA Zed board utilizing Verilog HDL in Xilinx Vivado.

A Sponge-Based Key Expansion Scheme for Modern Block Ciphers

Many systems in use today require strong cryptographic primitives to ensure confidentiality and integrity of data. This is especially true for energy systems, such as smart grids, as their proper operation is crucial for the existence of a functioning society. Because of this, we observe new developments in the field of cryptography every year. Among the developed primitives, one of the most important and widely used are iterated block ciphers. From AES (Advanced Encryption Standard) to LEA (Lightweight Encryption Algorithm), these ciphers are omnipresent in our world. While security of the encryption process of these ciphers is often meticulously tested and verified, an important part of them is neglected—the key expansion. Many modern ciphers use key expansion algorithms which produce reversible sub-key sequences. This means that, if the attacker finds out a large-enough part of this sequence, he/she will be able to either calculate the rest of the sequence, or even the original key. This could completely compromise the cipher. This is especially concerning due to research done into side-channel attacks, which attempt to leak secret information from memory. In this paper, we propose a novel scheme which can be used to create key expansion algorithms for modern ciphers. We define two important properties that a sequence produced by such algorithm should have and ensure that our construction fulfills them, based on the research on hashing functions. In order to explain the scheme, we describe an example algorithm constructed this way, as well as a cipher called IJON which utilizes it. In addition to this, we provide results of statistical tests which show the unpredictability of the sub-key sequence produced this way. The tests were performed using a test suite standardized by NIST (National Institute for Standards and Technology). The methodology of our tests is also explained. Finally, the reference implementation of the IJON cipher is published, ready to be used in software. Based on the results of tests, we conclude that, while more research and more testing of the algorithm is advised, the proposed key expansion scheme provides a very good generation of unpredictable bits and could possibly be used in practice.

Constructing Strong S-Box by 2D Chaotic Map with Application to Irreversible Parallel Key Expansion

Cryptanalysis of key expansion algorithms in AES and SM4 revealed that (1) there exists weaknesses in their S-Boxes, and (2) the round key expansion algorithm is reversible, i.e. the initial key can be recovered from any round key, which may be explored by the attacker. To solve these problems, first we constructed a nondegenerate 2D exponential hyper chaotic map (2D-EQCM), derived a recursion formula to calculate the number of S-Boxes, and designed a strong S-Box construction algorithm without such weakness. Then based on 2D-EQCM and S-Box, we designed an irreversible parallel key expansion algorithm, which could transform the initial key to any number of relatively independent round keys. Security and statistical analysis demonstrated the flexibility and effectiveness of the proposed irreversible parallel key expansion algorithm.

Isolation and expansion of murine γδ T cells from mouse splenocytes

Elucidation of the function of gamma delta T cells (γδ T cells) requires robust models that show how γδ T cells are commonly involved in inflammation, since very little is known about the factors that promote and control their development and function. There are few studies of murine γδ T cells primarily because these cells have proven difficult to isolate, expand and characterize. Here, we describe a simple method that utilizes key expansion elements to isolate and expand murine CD4−CD8−CD3+ γδ T cells typically found in secondary lymphoid tissues. Expansion of γδ T cells reached 150-fold by day 8 of culture, depended on exogenous IL-2, αCD3, and αCD28, and supported efficient and reproducible in vitro differentiation. These studies showed high production of cytokines IFNγ and Granzyme B, with the novel finding of IL-24 upregulation as well. Expression analysis of expanded γδ T cells, after treatment with IL-2, revealed high levels of Granzyme B, Granzyme D, and IFNγ. Lactate dehydrogenase (LDH) cytotoxicity assays showed that expanded γδ T cells were effective at inducing >90% cytolysis of murine MC38 colon cancer, E0771 breast cancer, and B16 melanoma cells at 10:1 effector to target ratios. These findings indicated that murine γδ T cells can be successfully isolated, expanded, and used to perform preclinical therapy studies.

Optimization and Design of Key Expansion of SM4 Algorithm Based on ZYNQ

As the application of "China Intelligent Manufacturing" in the field of production becomes more and more extensive, it becomes crucial to ensure the security of information interaction between production equipment. China's domestic encryption algorithm - SM4 block encryption algorithm came into being. The algorithm consists of a key expansion function and an encryption and decryption function. The key expansion function collects 128-bit keys at a time, and generates thirty-two 32-bit encryption keys after XOR operation, nonlinear permutation operation (S-box) and linear shift operation.The XOR operation parameter CK of the original key expansion function is obtained by the modulo method, which is similar to the system parameter FK and is a fixed value. In order to reduce the risk of deciphering caused by fixed parameters, the lightweight two-dimensional chaos algorithm Hemon is introduced for optimization design. The system parameters used in the SM4 algorithm are randomly generated with the change of the key, which improves the security of the algorithm. And use the hardware encryption platform ZYNQ-7000 series model xc7z100ffv900-1 FPGA side design and implementation, relying on the hard to decipher of hardware encryption to complete the optimization of SM4 algorithm key exchange.

Hiding data inside images using orthogonal moments

In this contribution we propose a novel steganographic method based on several orthogonal polynomials and their combinations. The steganographic algorithm embeds a secrete message at the first eight coefficients of a high frequency image. Moreover, this embedding method uses the Beta chaotic map to determine the order of the blocks where the secret bits will be inserted. In addition, from a 128-bit private key and the steps of a cryptography algorithm according to the Advanced Encryption Standard (AES) to generate the key expansion, the proposed method generates a key expansion of 2560 bits, with the purpose to permute the first eight coefficients of high frequency before the insertion. The insertion takes eventually place at the first eight high frequency coefficients in the transformed orthogonal moments domain. Before the insertion of the message the image undergoes a series of transformations. After the insertion the inverse transformations are applied to the original transformations in reverse order. The experimental work on the validation of the algorithm consists of the calculation of the Peak Signal-to-Noise Ratio (PSNR), the Universal Image Quality Index (UIQI), the Image Fidelity (IF), and the Relative Entropy (RE), comparing the same characteristics for the cover and stego image. The statistical undetectability of the proposed method is evaluated by using a blind steganalysis. The proposed algorithm improves the level of imperceptibility and security analyzed through the PSNR and RE values, respectively, and thus demonstrated resistance to steganalysis.

Construction of a Nondegenerate 2D Chaotic Map with Application to Irreversible Parallel Key Expansion Algorithm

The key expansion algorithm is an important part of a general iterated block cipher, because its security determines the security level of the encryption scheme. Thus, generating secure round keys with statistical independence and sensitivity is desirable. An irreversible parallel key expansion algorithm is proposed based on a chaotic map in this paper. First, an enhanced nondegenerate 2D exponential chaotic map (2D-ECM) with ergodicity is constructed, with analysis results demonstrating that it has better dynamical characteristics. Then, an irreversible key expansion algorithm is designed based on the 2D-ECM, which has high sensitivity to initial key with independence between round keys. Experimental results and performance analysis demonstrate that the algorithm is feasible and can resist the side channel power attack.

Efficient PPA Nano AES for IoT Applications

Abstract: Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable gate array (FPGA) and 65-nm technology for resource-constrained IoT devices. The proposed architecture includes 8-bit data path and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. To reduce the area, Shift-Rows is embedded inside the State-Register. To adapt the Mix-Column to 8-bit data path, we design an optimized 8-bit block for Mix-Columns with four internal registers, which accept 8-bit and send back 8-bit. Also, a shared optimized Sub-Bytes is employed for the key expansion phase and encryption phase. To optimize Sub-Bytes, we merge and simplify some parts of the Sub-Bytes. To reduce power consumption, we apply the clock gating technique to the design. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results, the proposed design is a suitable cryptosystem for tiny IoT devices. Keywords: IOT, Clock gating technique, ASIC

Development and analysis of the new hashing algorithm based on block cipher

This paper proposes the new hash algorithm HBC-256 (Hash based on Block Cipher) based on the symmetric block cipher of the CF (Compression Function). The algorithm is based on the wipe-pipe construct, a modified version of the Merkle-Damgard construct. To transform the block cipher CF into a one-way compression function, the Davis-Meyer scheme is used, which, according to the results of research, is recognized as a strong and secure scheme for constructing hash functions based on block ciphers. The symmetric CF block cipher algorithm used consists of three transformations (Stage-1, Stage-2, and Stage-3), which include modulo two addition, circular shift, and substitution box (four-bit S-boxes). The four substitution boxes are selected from the “golden” set of S-boxes, which have ideal cryptographic properties. The HBC-256 scheme is designed to strike an effective balance between computational speed and protection against a preimage attack. The CF algorithm uses an AES-like primitive as an internal transformation. The hash image was tested for randomness using the NIST (National Institute of Standards and Technology) statistical test suite, the results were examined for the presence of an avalanche effect in the CF encryption algorithm and the HBC-256 hash algorithm itself. The resistance of HBC-256 to near collisions has been practically tested. Since the classical block cipher key expansion algorithms slow down the hash function, the proposed algorithm is adapted for hardware and software implementation by applying parallel computing. A hashing algorithm was developed that has a sufficiently large freedom to select the sizes of the input blocks and the output hash digest. This will make it possible to create an almost universal hashing algorithm and use it in any cryptographic protocols and electronic digital signature algorithms

Design an irreversible key expansion algorithm based on 4D memristor chaotic system

Design an irreversible key expansion algorithm based on 4D memristor chaotic system

Quantum-key-expansion protocol based on number-state-entanglement-preserving tensor network with compression

Quantum-key-distribution (QKD) protocols allow exchanging a cryptographic key between two parties. With the development of the Internet, however, all forms of communications consume a huge number of cryptographic keys. Improving the secure key rate of QKD is becoming increasingly important. Quantum compression and key expansion are two ways to increase the secure key rate. In this paper, we propose a quantum-key-expansion (QKE) protocol. A series of singlet states are compressed by number-state-entanglement-preserving tensors and disentanglers to obtain a compressed two-body-entangled state. The cryptographic key is expanded by the number-state-entanglement-preserving tensor network. The advantages of the proposed QKE protocol over the classical-key-expansion algorithm in the key-expansion method, the key length, and the security are discussed in this study. Moreover, due to the structure of the number-state-preserving compression tensor network, our protocol can resist the intercept-resend attack, entanglement-and-measurement attack, and coherent attack.

LPsec: a fast and secure cryptographic system for optical connections

High capacity and low latency of optical connections are ideal for supporting current and future communication services, including 5G and beyond. Although some of those services are already secured at the packet layer using standard stream ciphers, like the Advanced Encryption Standard and ChaCha, secure transmission at the optical layer is still not implemented. To secure the optical layer, cryptographic methods need to be fast enough to support high-speed optical transmission and cannot introduce significant delay. Moreover, methods for key exchange, key generation, and key expansion are required, which can be implemented on standard coherent transponders. In this paper, we propose Light Path SECurity (LPsec), a secure cryptographic solution for optical connections that involves fast data encryption using stream ciphers and key exchange using Diffie–Hellman protocol through the optical channel. To support encryption of high-speed data streams, a fast, general-purpose pseudorandom number generator is used. Moreover, to make the scheme more secure against exhaustive search attacks, an additional substitution cipher is proposed. In contrast to the limited encryption speeds that standard stream ciphers can support, LPsec can support high-speed rates. Numerical simulation for 16 quadrature amplitude modulation (QAM), 32-QAM, and 64-QAM show that LPsec provides a sufficient security level while introducing only negligible delay.

Skew key polynomials and a generalized Littlewood–Richardson rule

Young’s lattice is a partial order on integer partitions whose saturated chains correspond to standard Young tableaux, one type of combinatorial object that generates the Schur basis for symmetric functions. Generalizing Young’s lattice, we introduce a new partial order on weak compositions that we call the key poset. Saturated chains in this poset correspond to standard key tableaux, the combinatorial objects that generate the key polynomials, a nonsymmetric polynomial generalization of the Schur basis. Generalizing skew Schur functions, we define skew key polynomials in terms of this new poset. Using weak dual equivalence, we give a nonnegative weak composition Littlewood–Richardson rule for the key expansion of skew key polynomials, generalizing the flagged Littlewood–Richardson rule of Reiner and Shimozono.

Implementation of a High-Speed and High-Throughput Advanced Encryption Standard

Data security is an essential aspect of data communication and data storage. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. Several modifications have been made to the original architecture after it was proposed by two Belgian researchers, Joan Daemen and Vincent Rijment, at the third AES candidate Conference in 2000. The existing modifications aim to increase security and speed. This paper proposes an efficient pipelined architecture for the key expansion process, effectively reducing the propagation delay to generate the required subkeys. Along with the pipeline structure, the fork and join architecture is also used in the key expansion part of the AES architecture, and it significantly reduces the time taken to generate the required subkeys. The proposed architecture is simulated and implemented on Xilinx Virtex4 XC4VLX200 FPGA. The result indicates that the proposed architecture achieves an improvement of about 37% in throughput compared with the original architecture. Also, the proposed architecture can convert the given plain text to cipher with a minimal propagation delay.

Implementation of area-efficient AES using FPGA for IOT applications

The increase in internet technology has made the number of devices connected to the internet increase day by day. The information transferred over the electronic media is vulnerable to security attacks. To protect the information, the data transferred over the internet should be encrypted. Therefore, it is essential to design the encryption architecture which is suitable for the resource constrained devices. FPGA implementation of area-efficient AES encryption algorithm is presented in this work. The proposed architecture includes 8-bit data path which reduces the number of internal wires. There are two register banks, the state register and the key register, which are used for storing intermediate results along with performing the operations in encryption and key expansion phase which reduces the area. Substitute bytes operation is implemented using ROM based LUT structure. The mix columns operation with 8-bit data path is realised using the four internal registers. This reduces area which is suitable for IOT applications which is the primary objective.

Secure and Efficient Implicit Certificates: Improving the Performance for Host Identity Protocol in IoT

Implicit certificates own the shorter public key validation data. This property makes them appealing in resource-constrained IoT systems where public-key authentication is performed very often, which is common in Host Identity Protocol (HIP). However, it is still a critical challenge in IoT how to guarantee the security and efficiency of implicit certificates. This article presents a forgery attack for the Privacy-aware HIP (P-HIP), and then propose a Secure and Efficient Implicit Certificate (SEIC) scheme that can improve the security of the P-HIP and the efficiency of elliptic-curve point multiplications for IoT devices. For a fix-point multiplication, the proposed approach is about 1.5 times faster than the method in SIMPL scheme. Furthermore, we improve the performance of SEIC with the butterfly key expansion process, and then construct an improved P-HIP. Experimental results show that compare to the existing schemes, the improved scheme makes a user/device have both the smallest computation cost and the smallest communication cost.

Lightweight and Low-Latency AES Accelerator Using Shared SRAM

In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, the proposed AES accelerator is located within the slave wrapper of the static random-access memory (SRAM) and is directly attached to the SRAM. Hence, the AES accelerator can directly access data in the SRAM and share SRAM space for storing expanded keys, resulting in no time for transferring input and output data, no resource usage for storing keys, and no power wastage for repeated key expansion. The proposed AES accelerator has a latency of 53 clock cycles per encryption/decryption process and has a gate count of 2912 when synthesized using 28 nm process technology. The latency is similar to that of another AES accelerator with the same 32-bit data path; however, the size of the proposed accelerator is 46.0% smaller. Furthermore, compared with other AES accelerators with 8-bit data path, the proposed AES accelerator has a 3.0–22.0 times smaller latency with a slightly larger area.

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data.

Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

DNA Cryptography Using DNA Fragment Assembly and Fragment Key Expansion for Genomic Data

This research proposes a tweaked scheme based on DNA fragment assembly to improve protection over insecure channel. The proposed procedure utilizes binary coding to change over an underlying plaintext into a reference DNA arrangement to deal with the fragmentation. DNA fragment key expansion is applied over the reference DNA sequence to make the short-chain fragments. The redundancy in the long-chain of reference DNA is removed using DNA fragment assembly. A look-up table is generated to store the binary values of overlapped fragments to be reassembled during the encryption and decryption processes to prevent artefacts. Also, it is used in an overlapped sequence to counteract cipher decomposition. The results and comparisons demonstrate that the proposed scheme can balance the three most important characteristics of any DNA masking scheme: payload, capacity, and BPN. Moreover, the potential for cracking the proposed tweaked method is more complex than the current strategies.