Kbytes Of Memory Research Articles

ARTK: a compact real-time kernel for Arduino

This article describes ARTK, a compact real-time kernel for the Arduino embedded systems development environment. It provides a priority-driven preemptive task scheduler, semaphores for task synchronisation, and serial channel output. It is compatible with Arduino boards containing more or less than 64 kbytes of memory. The memory footprint of ARTK is under 8 kbytes.

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hardware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

Embedded software optimization for MP3 decoder implemented on RISC core

This paper proposes general software optimization techniques for embedded systems based on processors, which mainly include general optimization methods in high language and software and hardware co-optimization in assembly language. Then these techniques are applied to optimize our MP3 decoder, which is based on RISC32, a RISC core compatible with MIPSI instruction set. The last optimization decoder requires 48 MIPS and 49 Kbytes memory space to decode 128 Kbps, 44.1 KHz joint stereo MP3 in real time with CPI 1.15, and we have achieved performance increase of 46.7% and memory space decrease of 38.8% over the original decoding software.

A precompliance EMC test-set based on a sampling oscilloscope

In this paper, a precompliance test-set for the measurement of conducted emissions based on a medium-level sampling oscilloscope and on a fast filtering algorithm (DFT) is presented. This system has been designed as a low-cost alternative to the typical precompliance test-sets that are based on spectrum analyzers equipped with EMC filters and peak detectors. Experimental examples of the results obtained using a sampling oscilloscope with 8 Kbytes of memory are given.

Counting the number of active flows on a high speed link

Internet links operate at high speeds, and past trends predict that these speeds will continue to increase rapidly. Routers and Intrusion Detection Systems that operate at up to OC-768 speeds (40 Gigabits/second) are currently being developed. In this paper we address a basic function common to several security and measurement applications running at line speeds: counting the number of distinct header patterns (flows) seen on a high speed link in a specified time period. For example one can detect port scans by counting the number of connections opened by the suspected port scanner and one can ascertain that a denial of service attack is in progress by counting the number of distinct (fake) source addresses that send packets to the suspected victim. We provide algorithms solving the flow counting problem using extremely small amounts of memory. This can translate into savings of scarce fast memory (SRAM) for hardware implementations. It can also help systems that use cheaper DRAM to allow them to scale to larger instances of the problem. The reduction in memory is particularly important for network security applications such as detecting port scans and DoS attacks that need to run a separate instance of the algorithm for each suspected attacker or victim. Our algorithms can be implemented in hardware at wire speeds (8 nsec per packet for OC-768) using simple CRC based hash functions, multiplexers and SRAM. They access at most one or two memory locations per packet. We expose the behavior of simple building blocks and provide a family of customizable counting algorithms that can be adapted to the requirements of various applications. This allows our algorithms to use less memory than the best known counting algorithm, probabilistic counting, to provide the same accuracy.• Virtual bitmap is well suited for triggers (which need only be accurate around a threshold value) such as detecting DoS attacks, and uses 292 bytes to achieve an error of 2.619% compared to 5,200 bytes for probabilistic counting.• Our "no assumptions" counting algorithm, multiresolution bitmap algorithms uses only 2143 bytes to count up to 100 million flows with an average error of 3%. Its accuracy is slightly better when the number of flows is small, while the accuracy of probabilistic counting using the same memory is much worse.• Our adaptive bitmap that exploits stationarity in the number of flows can count the number of distinct flows on a link that contains anywhere from 0 to 100 million flows with an average error of less than 1 % using only 2 Kbytes of memory. Probabilistic counting needs eight times more memory to achieve the same accuracy.• We used our triggered bitmap to replace the port scan detection component of the popular intrusion detection system Snort. Doing so reduced the memory usage from 89 Mbytes to 6.4 Mbytes (with an average error of 13.5%) as measured on a 10 minute trace. Probabilistic counting uses 23 Mbytes.This work was made possible by a grant from NIST for the Sensilla Project.

Novel detection of conics using 2-D Hough planes

The authors present a new approach to the use of the Hough transform for the detection of ellipses in a 2-D image. In the proposed algorithm, the conventional 5-D Hough voting space is replaced by four 2-D Hough planes which require only 90 kbytes of memory for a 384/spl times/256 image. One of the main differences between the proposed transform and other techniques is the way to extract feature points from the image under question. For the accumulation process in the Hough domain, an inherent property of the suggested algorithm is its capability to effect verification. Experimental results from the authors' work on real and synthetic images show that a significant improvement of the recognition is achieved as compared to other algorithms. Furthermore, the proposed algorithm is applicable to the detection of both circular and elliptical objects concurrently.

A 1 GHz flash-ADC module in VMEbus

A data acquisition module based on monolithic high-speed flash-analog-to-digital-converter-chips is described. Four fully independent channels, with 250 MHz sampling rate and a 2 kbyte buffer memory each, can be combined (interleaved) in one channel to achieve an effective 1-GHz sampling rate with a total of 8 kbyte memory depth. The double Eurocard board supports standard 16-b or 32-b VMEbus protocol for high-speed readout. The board is essentially self-contained and can be used cost-effectively in small applications and in large experimental setups. The performance of the data acquisition module has been tested.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Kinematic modeling of cross-sectional deformation sequences by computer simulation: coding and implementation of the algorithm

The structure and code of a kinematic algorithm is presented for the cross-sectional simulation of deformation by simple shear or fault-related, angular parallel folding. The algorithm executes a defined deformation path, given an initial structural geometry and stratigraphic layering. The undeformed medium is represented by an approximating body of finite quadrilateral elements. Analytically defined displacement functions are evaluated for the grid nodes.The algorithm is coded in Turbo-Pascal for implementation on a 640-kbyte-memory 80286 IBM-PC with 80287 coprocessor. Commercial subroutines provide graphical displays and windowing. The interactive program creates a mesh of up to 40 rows and 100 columns, which occupies 150 kbyte of memory. The deformed mesh is graphed in several overlapping windows which can be reduced or amplified. Frames can be saved on disk or printed.

A search-match program for materials identification in the Transmission Electron Microscope using electron diffraction pattern analysis

A program has been written for an energy dispersive x-ray microanalysis system computer to identify a sample by combining data from an electron diffraction pattern collected in a TEM with chemical information from the sample. The combined information is compared with a large database held on the computer to find a suitable set of matching compounds.The program was written for a Link Analytical AN10000 microanalysis system which is based on a computer with a 16 bit word length, 20 MHz CPU with 512 kbyte of memory for programs and data, 40 Mbyte hard disk and a 512 × 512 pixel colour image display with its own memory. The database used was the NBS/SANDIA/ICDD electron diffraction database adapted for the AN 10000 computer. This database contains about 70000 compound entries and occupies 9 Mbyte of disk space.

A unique application specific MCU for handheld data bank and terminals

An application-specific microcomputer unit (MCU) which implements all the necessary features of high-speed data bus, low power consumption, large memory addressability, and LCD (liquid crystal display) drive for battery-operated handheld terminal and personal data bank application is described. This device is an 8-bit CMOS MCU in a 128-pin quad flat pack. It has 27 I/O lines, 8-bit data and 16-bit address lines for 64 Kbytes memory access, real-time clock, 40 LCD front plane drives in 1/16 multiplexing mode, two system clocks, and an RS232-type serial communication port. >

A secondary and tertiary structure editor for nucleic acids.

A major difficulty in the evaluation of secondary and tertiary structures of nucleic acids is the lack of convenient methods for their construction and representation. As a first step in a study of the symbolic representation of biopolymers, we report the development of a structure editor written in Pascal, permitting model construction on the screen of a personal computer. The program calculates energies for helical regions, allows user-defined helices and displays the secondary structure of a nucleic acid based on a user-selected set of helices. Screen and printer outputs can be in the form of a backbone or the letters of the primary sequence. The molecule can then be displayed in a format which simulates its three-dimensional structure. Using appropriate glasses, the molecule can be viewed on the screen in three dimensions. Other options include the manipulation of helices and single-stranded regions which results in changes in the spatial relationship between different regions of the molecule. The editor requires an IBM or compatible PC, 640 kbyte memory and a medium or high resolution graphics card.

Technical note The use of a microcomputer for image analysis

Abstract An inexpensive microcomputer system has been configured to process and display Landsat-MSS digital data for higher education establishments. The system consists of a 16-bit processor with a maths co-processor, a 512 kbyte memory with 20Mbyte fixed disk drive, 1·2 Mbyte diskette drive, keyboard and enhanced colour monitor. A graphic development tool kit is installed to display an image. To enable data transfer to and from the mainframe computer, communication software is made available on both the microcomputer and the mainframe. This local work station is capable of carrying out both graphic work and image processing.

Materials for High Speed Circuit Boards

During the past five years, the computer you bought with 128 Kbytes of memory has been upgraded by the availability of 40 Mbyte storage and modems which allow instant access to databases around the world. The continuing need to perform more complex missions for modern defense systems in more hazardous environments will call for substantially higher data rates than are available today.

PROBFIND: a computer program for selecting oligonucleotide probes from peptide sequences.

Synthetic oligonucleotides have proven to be extremely useful probes for screening cDNA and genomic libraries. Selection of the appropriate probe can be more easily and accurately achieved with the use of the computer program PROBFIND. The user enters the amino acid sequence from a file or from the keyboard, selects the minimum length allowed for the probe and the maximum allowable degeneracy. The computer prints a list of the sequences of potential probes which meet these minimum specifications and the location of the corresponding sequence in the protein to the screen and to a file. The user may modify the specifications for length and degeneracy at any time during the output of data, which allows for rapid selection of the desired probe. The program is interactive, accepts any file format with only a single modification of the file, is written in BASIC, and requires less than 6 kbytes of memory. This makes the program easy to use and adaptable even to unsophisticated microcomputers.

6800/6802 microprocessor emulation adapter

The HP64000 development system can only allocate a minimum of 1 kbyte of memory, when converting a 6800 emulation pod into a 6802/6808 emulator. This can restrict the amount of user RAM available. An adapter design is proposed to take account of this, using the 6810 chip. The construction and use of the adapter are discussed.

Computing an arithmetic constant related to the ring of Gaussian integers

We compute the analogue for Z [ i ] {\mathbf {Z}}[i] of Euler’s constant, that is δ = lim n → + ∞ δ n \delta = {\lim _{n \to + \infty }}{\delta _n} , where δ n = ( Σ 2 ⩽ k ⩽ n 1 / π r k 2 ) − log ⁡ n {\delta _n} = ({\Sigma _{2 \leqslant k \leqslant n}}1/\pi r_k^2) - \log n . For this purpose we give an estimate for \[ r k = min { r ⩾ 0 ; there exists z ∈ C such that card ( Z [ i ] ∩ D ¯ ( z , r ) ) ⩾ k } , {r_k} = \min \left \{ {r \geqslant 0;{\text {there exists}}\;z \in {\mathbf {C}}\;{\text {such that card}}({\mathbf {Z}}[i] \cap \bar D(z,r)) \geqslant k} \right \}, \] and we compute a great number of values of r k {r_k} .

A Microprocessor Based CAMAC Data Acquisition System for Use in High Energy Physics

A high energy physics CAMAC data acquisition system is described which consists of a Motorola 68000 microprocessor monoboard system interfaced to two Digital Equipment Corporation (DEC) UNIBUSes. The system can be replicated any number of times (n) as a peripheral device on a host UNIBUS. This allows for n parallel channels of DMA data acquisition on n auxiliary UNIBUSes each with a CAMAC branch driver and 256 Kbytes of memory. Thus, the system reduces the time required to acquire data by a factor of ~n and simultaneously increases the total memory buffer available to the host UNIBUS by a factor of n. Such a technique is useful at fixed target particle accelerators where data is collected at a high instantaneous rates for a small fraction (10-25%) of the overall cycle time.

An introduction to the mixed-layer probe

The paper describes a free-falling mixed-layer (ML) probe to measure depth, temperature, conductivity, horizontal water velocity gradient (shear) and solar radiation. Measurement effects introduced by the probe tilt and orientation are resolved using a flux-gate compass and a two-axis inclinometer. Sampling of all channels is carried out 50 times/s and the probe drop speed is 1 m/s. Raw data are acquired at depth intervals of 0.02 m and post-processed to give averaged values over 0.10 m scales. The probe is designed to resolve horizontal shears with vertical scales between 0.10 and 2 m. A 4 MHz Z-80A microprocessor with 4 kbytes of memory, together with an arithmetic processor chip, constitute the control and data processing section of the ML probe. A 12-bit analogue-to-digital converter and multiplexer provide the ability to digitise outputs from up to 16 analogue sensors, while four 50 MHz counters allow sensors with frequency outputs to be used. Power is supplied to the probe via a 100 m cable which also contains the data communication lines operating at 38 400 bits/s. A feature of the ML probe is the integration of custom and commercial electronic circuitry and sensors to provide the best characteristics at optimum cost.

Simulation of a desalination plant supplied by a photovoltaic array with management strategies*

This paper describes a program developed to simulate and assess the project of a stand-alone seawater desalination plant fed by a photovoltaic array. Objectives of the program are to: • Define the correct dimension for some critical subsystems' models of the plant • Validate some design solutions chosen a priori • Compare different operation management strategies. Simulation of a yearly run of the plant meets the above objec tives, provided suitable models of the system hardware and operation control procedures are available. The program de veloped includes three main sections: (1) models of the system's major components (some models fit the operational character istic of the component, others are limited to the component's transfer function); (2) a stochastic model for prediction of the daily availability of solar energy, based upon the Markov-chain algorithm; and (3) systems control logic. The program has been used to simulate the annual operation of the system under different management strategies. Realistic input data was taken from records of observations from a near by meteorological station. The output data was the performance of the system in terms of electrical energy and drinkable water production in the year. The program was written in Fortran V, run on a Univac 1100/60 computer, and it occupies 11 Kbytes of memory. The simulation of one year of plant operation, with hourly steps, requires 425 Kbytes of memory for input and output data - the computation time amounts to about 9 s. The main routines structure allows utilisation in more general simulation programs in the area of conversion of natural energy resources.