K-best Detection Research Articles

Orbital angular momentum multiplexing communication system over atmospheric turbulence with K-best detection

Orbital angular momentum multiplexing communication system over atmospheric turbulence with K-best detection

Adaptive Detection for Virtual MIMO System in Smart Home Environment

Smart home devices have received considerable attention recently due to the promise of a large number of applications. Researchers are stepping up research with the goal of creating a smarter, more convenient and more comfortable life. A wide range of smart home devices are being developed to improve signal reliability and stability. This paper comprehensively introduces the smart home and its application, MIMO system, and some methods of signal detection. On this basis, the main characteristics of K-Best detection method are introduced. At the end of this paper, we summarize the current smart home technology, and its development prospects are introduced in detail.

Novel Hybrid MIMO Detector for Spatial Multiplexed MIMO System

The need of data transmission has recently increased dramatically and the promising MIMO technology has been employed to preserve reliability. It can achieve exceptionally enhanced spectral proficiencies by adopting several antennas both at the source and the receiver. However, complexity of several detection schemes escalates because of tremendous increasing of customers and antennas. This paper proposes novel hybrid MIMO detection (NHMD) method to compromise the complexity and the hardware design challenges. The key objective is to develop a less-complex hybrid detection system to enhance hardware execution suitability without negotiating the performance of the bit error rate. The proposed NHMD method combines conventional linear detectors such as zero-force (ZF) and minimum mean square error (MMSE) with the K-best detector for quality enhancement. It introduces an optimal differential evolution (ODE) algorithm that selects detector using multiple constraints. Moreover, this method uses parallelism process to reduce the number of arithmetic logics. The proposed NHMD method has been done for different antenna configurations (2×2, 4×4) and implemented on Xilinx tool with different FPGA families. The simulation results confirm that NHMD method consumes less hardware’s, power and higher throughput without affecting BER performance.

A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing

This article presents an 8 × 8 lattice-reduction-aided (LRA) soft-output multiple-input multiple-output (MIMO) detector for Chinese enhanced ultrahigh throughput (EUHT) wireless local area network (LAN) standard. The preprocessing algorithm combining simplified-sorting Cholesky decomposition and low-complexity decoupled lattice reduction (LDLR) is proposed to reduce computational complexity and latency with parallelism improvement. In addition, K-best detection adopts a sorting-reduced strategy utilizing approximate ordered sequence. Compared with other published LRA K-best detection algorithms, simulation results show that our proposed algorithm has performance improvement. In addition, in order to save hardware resources, a folded K-best architecture and an optimized intermediate storage strategy are introduced. Furthermore, a fully pipelined VLSI architecture is designed in Semiconductor Manufacturing International Corporation (SMIC) 40-nm 1P9M technology to support the 8 × 8.64 -QAM MIMO-OFDM system. The detector can achieve 3.85-Gb/s data throughput at 641-MHz clock frequency with 0.71-μs latency. The proposed detector is competitive in terms of latency, throughput, and area efficiency to state-of-the-art works and can meet the data-rate requirement of the EUHT standard.

Fractional Order Darwinian Particle Swarm Optimization based K Best Detection Algorithm for Mimo Communication

This paper describes the hardware implementation prototype for the recent massive Multiple In and Out communication. In the entire MIMO communication system, decoder plays an important role in reducing the complexity of system. The objective is to recast the operating K-best detection methodology by forwarding the backwash wrapped up in organizing the path metrics to enhance aptness for the implementation of hardware with very durable BER performance. A 8x8 MIMO and 64 QAM FODPSO K-Best decoder using Schnorr-Euchner (SE) enumeration and new parameter Rlimit is proposed for reducing the complexity, thereby provides a better performance. The architecture for reducing the BER to 0.3 dB with list size K and Rlimit to 4 is designed for a word length of 16 bits. The proposed architecture is synthesized using XST in 45nm CMOS technology and coded in Verilog for a Maximum frequency of 181.8 MHz, 1090.8 Mbps through and a power consumption of 782mW and latency of 0.044𝝁s.

Design and Implementation of An Improved K-Best Detection Algorithm

In MIMO system, with high modulation order and large number of antennas, the complexity of the traditional K-Best detection algorithm is still high. For solving this problem, the theory of the inter-layer reservation in the algorithm is further extended, and propose a new child node expansion strategy which is based on Euclidean distance sorting. By reducing the access nodes, get a low-complexity improved algorithm.Considering the performance of the algorithm, a fast sorting QR decomposition based on SINR is introduced for the pre-detection preprocessing. The simulation proves that the improved algorithm performs well while reducing the complexity.Then design a parallel pipeline of the detector which is implemented by Xilinx XC7Z045 FPGA.The results show that this scheme performs well and has less hardware resource consumption. Now it has been applied to the LTE-A air interface monitoring instrument project.

VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation

Multiple-input multiple-output (MIMO) technology is envisaged to play an important role in future wireless communications. To this end, novel algorithms and architectures are required to implement high-throughput MIMO communications at low power consumption. In this paper, we present the hardware implementation of a modified K-best algorithm combining conventional K-best detection and low-complexity successive interference cancellation at different levels of the tree search. The detector is implemented using a fully-pipelined architecture, which detects one symbol vector per clock cycle. To reduce the power consumption of the entire receiver unit, costly symbol-rate operations such as multiplication are eliminated both within and outside the detector without any impact on the performance. The hardware implementation of the modified K-best algorithm achieves area and power reductions of 16% and 38%, respectively, compared with the conventional K-best algorithm implementation, while incurring a signal-to-noise ratio penalty of 0.3 dB at the target bit error rate. Post-synthesis analysis shows that the detector achieves a throughput of 3.29 Gbps at a clock frequency of 137 MHz with a power consumption of 357 mW using a 65-nm CMOS process, which compares favourably with the state-of-the-art implementations in the literature.

Hardware Efficient Architecture for Element-Based Lattice Reduction Aided K-Best Detector for MIMO Systems

Multiple-Input Multiple-Output (MIMO) systems are characterised by increased capacity and improved performance compared to the single-input single-output (SISO) systems. One of the main challenge in the design of MIMO systems is the detection of the transmitted signals due to the interference caused by the multiple simultaneously transmitted symbols from the multiple transmit antennas. Several detection techniques have been proposed in the literature in order to reduce the detection complexity, while maintaining the required quality of service. Among these low-complexity techniques is the Lattice Reduction (LR), which can provide good performance and significantly lower complexity compared to Maximum Likelihood (ML) detector. In this paper we propose to use the so-called Element-based Lattice Reduction (ELR) combined with K-Best detector for the sake of attaining a better Bit Error Ratio (BER) performance and lower complexity than the conventional Lenstra, Lanstra, and Lovasz (LLL) LR-aided detection. Additionally, we propose a hardware implementation for the ELR-aided K-Best detector for a MIMO system equipped with four transmit and four receive antennas. The ELR-aided K-Best detector requires an extra 18% increase in power consumption and an extra 20% in area overhead compared to a regular K-Best detector dispensing with ELR, where this increase in the hardware requirements is needed in order to achieve a 2 dB performance improvement at a bit error rate of 10−5.

Lattice-Reduction-Aided Breadth-First Tree Searching Algorithm for MIMO Detection

We propose a lattice-reduction (LR)-aided breadth-first tree searching algorithm for MIMO detection achieving near-optimal performance with very low complexity. At each level of the tree in the search, only the paths whose accumulated metrics satisfy a particular restriction condition will be kept as the candidates. Furthermore, the number of child nodes expanded on each parent node, and the maximum number of candidates preserved at each level, are also restricted, respectively. All these measures ensure the proposed algorithm reaching a preset near-optimal performance and achieving very low average and maximum computational complexity. Simulation results verify the proposed algorithm’s higher efficiency in terms of the performance/complexity tradeoff than the existing LR-aided K-best detectors and LR-aided fixed-complexity sphere decoders.

A novel Segregated K-Best detection algorithm for low complexity near optimal MIMO receivers

This paper addresses the problem of computational and hardware complexity in higher order constellation Multiple Input Multiple Output (MIMO) detectors. A novel Segregated K-Best detection (SKD) algorithm is proposed to serve as low complexity near optimal detector for MIMO receivers. The algorithm reduces detection complexity by choosing an optimal value of K depending upon the layer of traversal. This allows lesser number of nodes to be traversed leading to reduced complexity with only slight degradation in error rate performance. Hardware Descriptive Language (HDL) implementation of SKD is performed using ‘one symbol detection per cycle architecture’ and a compatible ‘sequential linear sort’ algorithm is proposed for sorting in SKD. The proposed design achieves a throughput as high as 802Mbps with latency of 19.83ns.

Two‐dimensional sorting algorithm for high‐throughput K‐best MIMO detection

This brief presents a novel two-dimensional parallel sorting algorithm for high-throughput K-best detectors utilised in multiple-input multiple-output (MIMO) systems. The proposed sorting algorithm enhances the throughput by sorting a data set in parallel and avoids the relatively long latency of the traditional algorithms. This is especially important in MIMO systems utilising high-order modulation schemes. The authors used the sorting algorithm in a K-best detector with variable K values at different layers of the search tree, which improves the bit error rate performance and reduces the computational complexity significantly. The detector using the sorting algorithm is designed and implemented in TSMC 90-nm CMOS technology for 4 × 4 64-QAM MIMO systems. Operating at 200 MHz, the detector's throughput is 1.2 Gbps. Its equivalent gate count is 182K.

Hardware Efficient Modified K-Best Symbol Detection Algorithm for Wireless MIMO Systems

This paper presents a novel tree-search based modified K-best algorithm and its hardware structure for spatially multiplexed wireless multiple-input multiple-output systems. The aim is to modify the existing K-best detection algorithm and to address the challenge involved in sorting of the path metrics to improve the suitability for hardware implementation while maintaining the BER performance. The proposed modified K-best algorithm results in reduction of 24% in path metric computations and the VLSI implementation of the modified K-best detector has been done for different antenna configurations and different constellations. Novel hardware architecture was proposed and the hardware complexity analysis was done. The proposed tree-search based modified K-best detector implemented on Xilinx Virtex 5 FPGA, targeting 4 × 4 antenna configuration with 16 QAM, achieves a constant throughput of 1 Gbps.

Reducing Computational Complexity and Enhancing Performance of IKSD Algorithm for Encoded MIMO Systems

<p>The main challenge in MIMO systems is how to design the MIMO detection algorithms with lowest computational complexity and high performance that capable of accurately detecting the transmitted signals. In last valuable research results, it had been proved the Maximum Likelihood Detection (MLD) as the optimum one, but this algorithm has an exponential complexity especially with increasing of a number of transmit antennas and constellation size making it an impractical for implementation. However, there are alternative algorithms such as the K-best sphere detection (KSD) and Improved K-best sphere detection (IKSD) which can achieve a close to Maximum Likelihood (ML) performance and less computational complexity. In this paper, we have proposed an enhancing IKSD algorithm by adding the combining of column norm ordering (channel ordering) with Manhattan metric to enhance the performance and reduce the computational complexity. The simulation results show us that the channel ordering approach enhances the performance and reduces the complexity, and Manhattan metric alone can reduce the complexity. Therefore, the combined channel ordering approach with Manhattan metric enhances the performance and much reduces the complexity more than if we used the channel ordering approach alone. So our proposed algorithm can be considered a feasible complexity reduction scheme and suitable for practical implementation.</p>

Low-Complexity Group Alternate Iterative List Detection for MIMO Systems

In this paper, we propose a low-complexity group alternate iterative list (GAIL) detection algorithm for MIMO systems. By utilizing the recursive interference suppression and successive interference cancellation techniques, the symbol vector can be partitioned into many subgroups. Subsequently, symbols in each subgroup are detected in terms of the K-best detector. The inter-group interference is effectively mitigated in the GAIL algorithm by creating a candidate list and iteratively correcting the unreliable symbols for the detection result. We provide the performance-complexity tradeoff based on different feasible parameter settings. The numerical results demonstrate that the GAIL algorithm can achieve close-to-optimal performance while maintaining low computational complexity. In addition, the running speed of the GAIL algorithm can be dramatically increased using parallel processing in real-time communication systems.

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing

This paper proposes a flexible dual-mode soft-output multiple-input multiple-output (MIMO) detector to support open-loop and closed-loop in Chinese enhanced ultra high throughput (EUHT) wireless local area network (LAN) standard. The proposed detector uses minimum mean square error (MMSE) sorted QR decomposition (MMSE-SQRD) to produce channel preprocessing result, which is realized by a modified systolic array architecture with concurrent sorting. Moreover, the adopted square-root MMSE algorithm for closed-loop reuses MMSE-SQRD preprocessing to largely save hardware overhead. In addition, an optimized K-Best detection algorithm is proposed for open-loop, which increases throughput by odd-even parallel sorting and produces high quality soft-output with discarded paths (DPs). A flexible VLSI architecture is designed for the proposed dual-mode detector, which supports $1\times 1\sim 4\times 4$ antennas and BPSK $\sim$ 64-QAM modulation configuration. Implemented in SMIC 65 nm CMOS technology, the detector is capable of running at 550 MHz, which has a maximum throughput of 2.64 Gb/s for K-Best detection and 3.3 Gb/s for linear MMSE detection. The proposed detector is competitive to recent published works and meets the data-rate requirement of the EUHT standard.

Sparse K ‐best detector for generalised space shift keying in large‐scale multiple‐input–multiple‐output systems

In this study, the authors propose a low complexity detector for the generalised space shift keying (GSSK) in large-scale multiple-input–multiple-output systems. To be concrete, they propose a sparse K-best (SK) detector based on the breadth-first category of sphere detector (referred to K-best sphere decoding). The author's detector is inspired by the fact that the GSSK signal is naturally a sparse zero-one vector since only a few antennas are activated at the transmitter. Different with the conventional K-best detector searching all the transmit antennas, their proposed SK detector investigates only a few promising candidates which are activated antennas at the transmitter. Overall, their proposed SK detector exploits not only the sparsity of the GSSK signal but also the constraint on its non-zero values. Therefore the restricted isometry property-based performance analysis shows that is effective in detecting the GSSK signal. Moreover, the empirical results show that their detector performs much better than the sparse algorithms-based normalised compressive sensing (NCS) detectors while exhibits only slightly higher complexity than the latter (the low-complexity orthogonal matching pursuit-based NCS detector).

Reduced-Complexity k-best Decoder for LTE Standard

This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard. In recent wireless communication system, MIMO technology is considered as the key technique in LTE to meet the target. Maximum Likelihood (ML) detection is the optimal detection algorithm for MIMO systems. FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas. Therefore, we propose a modified K-best detector algorithm which employs parallel and distributed sorting strategy combined with bitonic sorter that has near-ML detection solution. The design was implemented targeting Xilinx Spartan 6 device and the resource utilization results are presented and the performance comparison with the literature was also done. The total on-chip power estimated is 213mW.

A 3.1 Gb/s 8<inline-formula> <tex-math notation="LaTeX">$\,\times\,$ </tex-math></inline-formula>8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection system. The proposed system includes a QR decomposition, lattice reduction (LR) processor, and sorting-reduced (SR) K-best detector for 8 × 8 multiple-input multiple-output (MIMO) systems. The bit error rate of the proposed MIMO detection system only incurs approximately 3 dB of implementation loss compared with optimal maximum likelihood detection with 64-quadratic-amplitude modulation. The proposed processor can also support different throughput requirements by adjusting the stage number of LR. The SR K-best detector can achieve 3.1 Gb/s throughput with 0.24-ns latency. The throughput of the system reaches 585 Mb/s if one channel preprocessing can support 72 symbol detections. The corresponding energy per bit is 63 pJ/bit, which is the smallest value achieved to date. This paper presents the first VLSI implementation of a complete LRA K-best detector with an 8 × 8 dimension.

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems

In a broadband MIMO-OFDM wireless communication system, embedded buffering memories occupy a large portion of the chip area and a significant amount of power consumption. Due to process variations of advanced CMOS technologies, it becomes both challenging and costly to maintain perfectly functioning memories under all anticipated operating conditions. Thus, Voltage over Scaling (VoS) has emerged as a means to achieve energy efficient systems resulting in a tradeoff between energy efficiency and reliability. In this paper we present the algorithm and VLSI architecture of a novel error-resilient K-Best MIMO detector based on the combined distribution of channel noise and induced errors due to VoS. The simulation results show that, compared with a conventional MIMO detector design, the proposed algorithm provides up-to 4.5 dB gain to achieve the near-optimal Packet Error Rate (PER) performance in the 4 × 4 64-QAM system. Furthermore, based on experimental results, when jointly considering the detector and memory power consumption, the proposed resilient scheme with VoS memory can achieve up to 32.64% savings compared to the conventional K-Best detector with perfect memory.

Research on low-complexity breadth-first detection for multiple-symbol differential unitary space–time modulation systems

The breadth-first searching algorithms, typically represented by K-best algorithm, are widely studied for multiple-symbol differential detection in multiple-input multiple-output systems due to the advantages of fixed complexity and latency which are very attractive for hardware implementation. However, it needs a large K value to achieve near maximum likelihood performance, which results in large complexity. In this study, a dynamic K-best detection with reduced average K value is proposed. It reduces the complexity on path expanding, path updating and comparing and swapping (C&S) operations by 24.24, 25 and 43.46%, respectively, with less performance degradation. After that, two low-complexity sorting architectures, Batcher's merge sort and K cycles sort, are presented and applied to the proposed dynamic K-best detection. The complexity analysis and simulation results show that, compared with the traditional Bubble sorting dynamic K-best detection, the K cycles sorting and the Batcher's merge sorting dynamic K-best detections can further save C&S operations by 59.5 and 11.2%, respectively, while performance cost capable of being ignored. Moreover, the K cycles sorting dynamic K-best detection achieves best trade-off on throughput and required memory, and the architecture of the Batcher's merge sorting dynamic K-best detection is more beneficial to parallel processing and multiple-processor structure.