Abstract
This paper describes the hardware implementation prototype for the recent massive Multiple In and Out communication. In the entire MIMO communication system, decoder plays an important role in reducing the complexity of system. The objective is to recast the operating K-best detection methodology by forwarding the backwash wrapped up in organizing the path metrics to enhance aptness for the implementation of hardware with very durable BER performance. A 8x8 MIMO and 64 QAM FODPSO K-Best decoder using Schnorr-Euchner (SE) enumeration and new parameter Rlimit is proposed for reducing the complexity, thereby provides a better performance. The architecture for reducing the BER to 0.3 dB with list size K and Rlimit to 4 is designed for a word length of 16 bits. The proposed architecture is synthesized using XST in 45nm CMOS technology and coded in Verilog for a Maximum frequency of 181.8 MHz, 1090.8 Mbps through and a power consumption of 782mW and latency of 0.044𝝁s.
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