Junctionless Nanowire Transistors Research Articles

Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor

Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor

Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Differently from inversion mode MOS transistors, Junctionless Nanowires surface potential presents a strong dependence on the gate and drain biases, when the devices are biased in partial depletion. For that reason, the position of interface trap centers along the channel could have a significant influence on the electrical characteristics of the devices. Therefore, this work has evaluated how the position of a single interface trap along the channel can affect the low-frequency noise response of Junctionless Nanowire Transistors. It has been shown that the trap centers closer to the source side of the devices are more likely to degrade the noise characteristics than those located closer to the drain, which has been attributed to the lower surface potential in this region, enabling traps to be at the same state (occupied or empty) for a longer time interval.

Nanoscale Thermal Transport in Vertical Gate- All-Around Junctionless Nanowire Transistors— Part II: Multiphysics Simulation

Nanoscale Thermal Transport in Vertical Gate- All-Around Junctionless Nanowire Transistors— Part II: Multiphysics Simulation

Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods

Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current–voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs. We then incorporated these effects into the SPICE-compatible VNWFET compact model and further investigated the behaviors of trapping and electrothermal effects in basic logic circuits based on the compact model simulation.

(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models [1].As an important first step to access the intrinsic device characteristics, one must remove or ‘de-embed’ the parasitic contributions of external test structures and interconnections. However, for technologies such as the 3D VNWFET, precision of the S-parameter de-embedding step is crucial for accurate model parameter extraction. On the current fabricated VNWFET wafer, only open structures were available and the standard open de-embedding method led to inaccurate or even unphysical values of intrinsic capacitances. While one could design and fabricate additional de-embedding test structures to overcome this, to avoid another design cycle, a new dedicated de-embedding method was developed based on the modelling of the transistor interconnects, leveraging EM simulation [2]. After accurately calibrating the EM simulation against S-parameter measurements of the Open structure, virtual test structures of the same technological process, layout and material properties, were designed in the EM simulation environment. This included Open and Short structures at different reference planes that were simulated for extracting individual interconnect parasitic contributions. Next, the EM simulation served as a predictive tool to construct an electrical equivalent circuit of the entire 3D VNWFET interconnection network (Fig.1). Compared with conventional de-embedding techniques based on Open and Short measurements, the proposed interconnect network modelling-based approach relies on fewer test structures and can provide better accuracy, necessary for compact model parameter extraction.The DTCO is driven by the use of VNWFETs in highly compact 3D logic circuits. Design of these logic circuits relies heavily on compact models, containing a set of physics-based analytical equations for the juntionless transistors. The compact model developed for the 18 nm VNWFET technology [3] has been extensively validated against measurements depicting very good agreement over the entire bias range. To leverage the model for predictive design through DTCO, we further explored the scalability for all available transistor geometries that showed a visible improvement in current scalability for larger devices (Fig.2). However, process variation has limited linear current scaling in smaller nanowire diameters that are of more interest for junctionless transistor operation. In contrast, for a given number of parallel nanowires, maintaining gate electrostatic control over the channel in larger diameters becomes more difficult along with a degradation of the drain current on/off ratio, despite better current scaling (Fig.3). So as a design trade-off for the DTCO, we chose transistors with an optimal diameter (where junctionless functionality and gate electrostatic control are maintained for individual nanowires) with a higher number of nanowires in parallel to boost the drive current.Reliability assessment through electro-thermal measurements of VNWFETs is crucial when designing 3D logic circuits within DTCO framework, particularly for evaluating long-term performances and underlying transport mechanisms. Conventional methods for thermal investigation were not applicable for the VNWFETs as the drain current shows steady increase with temperature in contrast with classical devices (Fig.4). Since activation of self-heating could not be confirmed using traditional methods, a new methodology for thermal resistance estimation in VNWFETs is developed. This relies on the intersecting points on ID-VG curves at different measurement temperatures (TA) and power dissipations (Pdiss) corresponding to same VG and ID. From the ratio of junction temperatures (Tj=TA+RTH*Pdiss) for the two sets of intersecting curves related to different VD and threshold voltages and subsequent calculations, thermal resistances (RTH) were extracted. Theoretical calculations corroborated extracted results with RTH values ranging between 4 and 28×104 K/W. Other non-conventional methods were also explored such as low-frequency S-parameter measurements or RTH extraction using the slope of drain current versus temperature plot at different dissipated powers, all of which offered similar results even though measurement uncertainties related to each method should be carefully accounted for. A final verification using full device thermal simulation in COMSOL multiphysics, accounting for both ballistic and diffusive heat flux, showed fair agreement with experimental results. This is the first demonstration of thermal resistance extraction in highly-scaled VNWFETs. Figure 1

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.

Junctionless nanowire transistors effective channel length extraction through capacitance characteristics

This work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.

Dopant segregation effects on ohmic contact formation in nanoscale silicon

The impact of boron dopant segregation on the carrier density in silicon nanowires and ohmic contact formation is studied. Based on electrical measurements of individual nanowires and a secondary ion mass spectroscopy study, we show that an oxidation at high temperatures reduces the active carrier density of the silicon nanowires due to the onset of dopant segregation. On the other hand, improved ohmic contact resistivities as low as 6E-7 Ω⋅cm2 is achieved by dopant surface segregation during the thermal formation of platinum silicided contacts. We show, that the contact resistivity decreases with increasing contact pad area for silicided, as well as non-silicide nanowires. Furthermore, it is also demonstrated that the achieved ohmic contacts can be used to realize junctionless nanowire transistors.

(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.

(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement

In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is confirmed from deep depletion to accumulation and from linear to saturation, based on the numerical solution of the Schrödinger equation using Technology Computer Aided Design (TCAD) simulations. This represents an important stage toward AC small signal analysis of junctionless nanowire-based circuits.

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO2 interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 1012 cm–2 and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.

Interface traps density extraction through transient measurements in junctionless transistors

This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.

Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

This paper proposes hafnium (IV) oxide (HfO2) as gate oxide material of the nanowire junctionless transistor (NJT) to replace the conventional silicon dioxide (SiO2). Leakage current usually increased due to an increase of tunneling of electronsin SiO2transistor when the thickness oxide (tox) of the gate material is below 2nm. The main advantages of HfO2is high dielectric constant k of 20 to 25 which is almost 6 times than that of SiO2. Similarly, HfO2has an energy band gap of 5.3 to 5.7eV. As a result, low leakage current and short channel effects (SCEs) was experienced. An increased in the gate capacitance of the device leads to improve the performance of the device without affecting the enhanced leakage current. All these was achieved by designing and simulating the device using the SDE tools of Sentaurus TCAD. Electrical characteristics was extracted using the Sdevice tools of the software. The performance was significantly increased to approximately 1010using HfO2material

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

We investigate the influence of source and drain bias voltages (V DS) on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K. We demonstrate that the transverse electric field introduced from V DS has a minor influence on the threshold voltage of the device. The transverse electric field plays the role of amplifying the gate restriction effect of the channel. The one-dimensional (1D)-band dominated transport is demonstrated to be modulated by V DS in the saturation region and the linear region, with the sub-band energy levels in the channel (E channel) intersecting with Fermi levels of the source (E fS) and the drain (E fD) in turn as V g increases. The turning points from the linear region to the saturation region shift to higher gate voltages with V DS increase because the higher Fermi energy levels of the channel required to meet the situation of E fD = E channel. We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel, equivalent to the effect of thermal temperature on the increase of electron energy. Our work provides a detailed description of the bias-modulated quantum electronic properties, which will give a more comprehensive understanding of transport behavior in nanoscale devices.

Charge-based modeling of ultra narrow junctionless cylindrical nanowire FETs

This brief proposes an analytical approach to model the DC electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistors (JL-NW-FETs). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave-functions obtained by the Schrödinger equation in the cylindrical-coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits, mainly biosensors based on junctionless nanowire transistors.

Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.