Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Abstract

Differently from inversion mode MOS transistors, Junctionless Nanowires surface potential presents a strong dependence on the gate and drain biases, when the devices are biased in partial depletion. For that reason, the position of interface trap centers along the channel could have a significant influence on the electrical characteristics of the devices. Therefore, this work has evaluated how the position of a single interface trap along the channel can affect the low-frequency noise response of Junctionless Nanowire Transistors. It has been shown that the trap centers closer to the source side of the devices are more likely to degrade the noise characteristics than those located closer to the drain, which has been attributed to the lower surface potential in this region, enabling traps to be at the same state (occupied or empty) for a longer time interval.