Junctionless Mode Research Articles

Analysis of coupling effect between TID and SET in SOI Tri-Gate nanowire field-effect transistors

This study investigates the response of nanowire field-effect transistors (NWFETs) to total ionizing dose (TID), single-event transient (SET), and their coupling effects in junctionless (JL), inversion (IM), and junctionless accumulation (AC) modes. The degradation of the three modes under irradiation and the effect of device bias configuration on the electrical properties of NWFETs are analyzed, and the different effects of SET on the three modes are compared. On this basis, the influence of TID on SET current generation and the charge collection mechanism are studied, and the changes in peak current, pulse width, and collected charge of transient current under different TIDs are compared. The results show that JL mode has the worst resistance to TID and SET coupling effects, followed by IM and AC modes.

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit.[1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

Role of Junctionless Mode in Improving the Photosensitivity of Sub-10 nm Carbon Nanotube/Nanoribbon Field-Effect Phototransistors: Quantum Simulation, Performance Assessment, and Comparison.

In this article, ultrascaled junctionless (JL) field-effect phototransistors based on carbon nanotube/nanoribbons with sub-10 nm photogate lengths were computationally assessed using a rigorous quantum simulation. This latter self-consistently solves the Poisson equation with the mode space (MS) non-equilibrium Green’s function (NEGF) formalism in the ballistic limit. The adopted photosensing principle is based on the light-induced photovoltage, which alters the electrostatics of the carbon-based junctionless nano-phototransistors. The investigations included the photovoltage behavior, the I-V characteristics, the potential profile, the energy-position-resolved electron density, and the photosensitivity. In addition, the subthreshold swing–photosensitivity dependence as a function of change in carbon nanotube (graphene nanoribbon) diameter (width) was thoroughly analyzed while considering the electronic proprieties and the quantum physics in carbon nanotube/nanoribbon-based channels. As a result, the junctionless paradigm substantially boosted the photosensitivity and improved the scaling capability of both carbon phototransistors. Moreover, from the point of view of comparison, it was found that the junctionless graphene nanoribbon field-effect phototransistors exhibited higher photosensitivity and better scaling capability than the junctionless carbon nanotube field-effect phototransistors. The obtained results are promising for modern nano-optoelectronic devices, which are in dire need of high-performance ultra-miniature phototransistors.

A novel circular double-gate SOI MOSFET with raised source/drain

In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or top and bottom (both). The results demonstrate that the best device configuration is a raised both CDGT with an internal pad as a drain. For the above configuration, the impact of a junctionless mode is further analyzed and the optimum performance is obtained with a doping level of 1 × 1018 cm−3. The device exhibits good electrical characteristics, with an ON/OFF current ratio of 3.73 × 105, a near-ideal subthreshold slope of 66.9 mV dec−1, and a small drain-induced barrier lowering of ∼35 mV V−1. Among various circular MOSFETs, the CDGT device exhibits an optimum delay performance of 2 ps based on a two-stage inverter analysis.

Single Event Transients in Sub-10nm SOI MuGFETs Due to Heavy-Ion Irradiation

We compare and report in this work heavy-ion irradiation induced single event transients (SETs) in sub-10nm node SOI multiple gate FETs with the help of calibrated 3-D TCAD simulations. Our analysis includes the nanosheet FET (NSFET), nanowire FET (NWFET), and FinFET along with two different device design modes based on the doping profiles, namely the inversion (INV) and junctionless mode (JL). We have also analyzed the impact of heavy-ion strike direction and angle of incidence on SET performance of various MuGFETs. Heavy-ion induced SET current has also been compared for multiple-sheet/wires of NSFET and NWFET. In addition to this, different locations of heavy-ion strike have also been considered in this work. Further, we have collated the simulation trends to propose empirical models that predict the impact of heavy-ion radiation on various MuGFETs. Our models include some of the device design parameters and heavy-ion exposure conditions as the input to the model. The proposed models are shown to correlate well with the TCAD simulation results for the set of model parameters that we have reported here. These models not only expedite the analysis, but these can also accurately predict SETs in advanced MuGFETs under heavy-ion irradiation.

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

A Comparative Study on Hot-Carrier Injection in 5-Story Vertically Integrated Inversion-Mode and Junctionless-Mode Gate-All-Around MOSFETs

The hot-carrier degradation of the junctionless mode (JM) and the inversion mode (IM) of five-story vertically integrated gate-all-around (GAA) MOSFETs is investigated for the first time. It is found that the degradation of drain current induced by the hot-carrier injection (HCI) in the JM-FET is less than that in the IM-FET for the same dimensions and bias conditions, because of the bulk conduction mechanism of the JM-FET, which is in contrast to surface conduction of the IM-FET. The results are obtained using electrical measurements and numerical simulations. The analysis of how HCI affects the lifetime reliability of vertically integrated GAA MOSFETs is of great importance for ultimate scaling of the silicon transistor.

Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs

The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation. The simulated bulk Ge FinFET device exhibits favorable short channel characteristics, including drain-induced barrier lowering (DIBL<10 mV/V), sub threshold slope (SS∼64mV/dec.). Electron density distributions in ON-state and OFF-state also show that the simulated devices have large ION/IOFF ratios. Homogenous source/drain doping is maintained and only the channel doping is varied among different operating modes. Also, a constant threshold voltage |VTH| ∼ 0.31 V is maintained. Moreover, the calculated quantum capacitance (CQ) values of the Ge nanowire emphasizes the importance of quantum confinement effects (QCE) on the performance of the ultra-scaled devices.

Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs

Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device, which is based on the silicon–oxide–nitride–oxide–silicon (SONOS) configuration is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM). The LF noise showed 1/ $f$ –shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length

We investigated the device performance of the optimized 3-nm gate length (LG) bulk silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The subthreshold slope values (SS ~ 65 mV/decade) and drain-induced barrier lowering (DIBL <; 17 mV/V) are analyzed in all three IM, AC, and JL modes bulk FinFET with |VTH| ~0.31 V. Furthermore, the threshold voltage (VTH) of the bulk FinFET can be easily tuned by varying the work function. This letter reveals that Moore's law can continue up to 3-nm nodes.

High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure

Two types of fin-shaped field-effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heterojunction-free GaN layer operating in junctionless mode, have been fabricated and characterized. The threshold voltages of both devices shift toward positive direction from large negative value as the fin width decreases. Both devices exhibit high ON-state performance. The heterojunction-free GaN FinFETs show superior OFF-state performance because the current flows through the volume of the GaN channel layer, which can be fully depleted. The proposed GaN nanochannel FinFETs are very promising candidates not only for high performance, but also for high power applications.