Junction Termination Extension Research Articles

GaN-on-sapphire JTE-anode lateral field-effect rectifier for improved breakdown voltage (>2.5 kV) and dynamic RON

In high-power switching applications such as electric grids, transportation, and industrial electronics, power devices are supposed to have kilo-voltage (kV) level blocking capability. In this work, 1200-V gallium nitride (GaN) lateral field-effect rectifiers (LFERs) are demonstrated. The GaN-on-sapphire epitaxial structure is adopted to prevent vertical breakdown. To address electric field crowding, a p-GaN/AlGaN/GaN junction termination extension (JTE) is embedded in the anode region of the LFER. Comparing to the conventional LFER (Conv-LFER) fabricated on the same wafer, the JTE-anode LFER (JTE-LFER) achieves an improved breakdown voltage (>2.5 kV) and a lower dynamic ON-resistance (RON). The proposed p-GaN/AlGaN/GaN JTE offers a semiconductor-based solution (contrasted to the dielectric-based solution, i.e., field plate) to mitigate the high electric field, which is highly desirable for wide bandgap semiconductor power devices as it enhances the dielectric reliability.

Study on the Impact of Mg-Channeled Implantation on Junction Termination Extension for GaN Vertical Power Devices Using TCAD Simulation

Study on the Impact of Mg-Channeled Implantation on Junction Termination Extension for GaN Vertical Power Devices Using TCAD Simulation

Expanding the dose window of step-etched space-modulated JTE for ultrahigh voltage 4H-SiC devices

A step-etched space-modulated junction termination extension (SE-SM-JTE) is proposed for ultrahigh voltage (≥10 kV) 4H-SiC devices in this work. The proposed structure creates a stepped effective JTE dose profile by introducing the step etching into space-modulated JTE (SM-JTE), which shows great merits in the compromises of the JTE dose window, termination efficiency, termination area, and the complexity of the fabrication process. According to the TCAD simulation results, the SE-SM-JTE with a length of 300 μm (3 times the drift layer thickness) obtains a wide implantation dose window of ±47 % above 12 kV, achieving a wide tolerance to JTE dose and surface fixed charge. The maximum breakdown voltage (BV) of the proposed SE-SM-JTE is 13.8 kV, exhibiting a termination efficiency of 92 %. Moreover, the proposed JTE structure requires only a single ion implantation and subsequent two etchings, which facilitates the fabrication feasibility in ultrahigh voltage 4H-SiC devices.

Design and evaluation of β-Ga2O3 junction barrier schottky diode with p-GaN heterojunction

A novel design for a junction barrier Schottky (JBS) diode based on a p-GaN/n-Ga2O3 heterojunction is proposed, exhibiting superior static characteristics and a higher breakdown capability compared to the traditional Ga2O3 Schottky barrier diode (SBD). By utilizing wide-bandgap p-type GaN, the β-Ga2O3 JBS diodes demonstrate a turn-on voltage (V on ) of approximately 0.8 V. Moreover, a breakdown voltage (V br ) of 880 V and a specific on-resistance (R on,sp ) of 3.96 mΩ·cm2 are achieved, resulting in a Baliga’s figure of merit (BFOM) of approximately 0.2 GW /cm 2. A forward current density of 465 A cm−2 at a forward voltage of 3 V is attained. The simulated reverse leakage current density remains low at 9.0 mA cm−2 at 800 V. Floating field rings, in conjunction with junction termination extension (JTE), were utilized as edge termination methods to attain a high breakdown voltage. The impact of β-Ga2O3 periodic fin width fluctuations on the electrical characteristics of JBS was investigated. Due to the enhanced sidewall depletion effect caused by p-type GaN, the forward current (I F ) and reverse current (I R ) decrease when the β-Ga2O3 periodic fin width decreases. The findings of this study indicate the remarkable promise of p-GaN/n-Ga2O3 JBS diodes for power device applications.

A Novel Tapered Doping Tail Modulated Single Junction Termination Extension for High Voltage 4H-SiC Devices

A Novel Tapered Doping Tail Modulated Single Junction Termination Extension for High Voltage 4H-SiC Devices

The effects of different anode manufacturing methods on deep levels in 4H-SiC p+n diodes

The manufacture of bipolar junctions is necessary in many 4H-SiC electronic devices, e.g., junction termination extensions and p+in diodes for voltage class >10 kV. However, the presence of electrically active levels in the drift layer that act as minority charge carrier lifetime killers, like the carbon vacancy (VC), undermines device performance. In the present study, we compared p+n diodes whose anodes have been manufactured by three different methods: by epitaxial growth, ion implantation, or plasma immersion ion implantation (PIII). The identification of the electrically active defects in the drift layers of these devices revealed that a substantial concentration of VC is present in the diodes with epitaxial grown or ion implanted anode. On the other hand, no presence of VC could be detected when the anode is formed by PIII and this is attributed to the effects of strain in the anode region. Our investigation shows that PIII can be a useful technique for the manufacture of bipolar devices with a reduced concentration of lifetime killer defects.

Multi-Step junction termination extension design and simulation study for 4H-SiC Schottky barrier diode

This paper presents a structure for designing Junction Termination Extension (JTE) in Silicon Carbide (SiC) power devices, particularly for Schottky Barrier Diodes (SBD). The P-type island composite multi-step JTE configuration has been developed by optimizing the number, length, and thickness of JTE steps. The JTE with step number of 4 and step length of 8 μm (SBD-n4L8) achieved a breakdown voltage of 1626 V at the same drift layer thickness of 10 μm, outperforming other step-based JTE structures. At reverse voltage of 1200 V, the SBD-n4L8 demonstrates a decrease in reverse leakage current with a uniform step-like current distribution profile. Subsequent analysis of the underlying mechanisms showed that, with step thickness of 2 μm, the SBD-n5L8 located at the corner and edge of the terminal region significantly reduced the peak electric field by more than 12.6 %.

Design Strategy of Vertical GaN Power Schottky Barrier Diodes with p‐GaN Junction Termination Extension and Experimental Demonstration of Selective p‐Doping by Implantation

Herein, the impact of the key structural parameters on the breakdown characteristics of the vertical gallium nitride (GaN) power Schottky barrier diodes (SBDs) with p‐GaN junction termination extension (JTE) structures by numerical simulation is systematically investigated. With a p‐type GaN structure incorporated at the edge of the Schottky junction, the electric field crowding at the edge of Schottky anode can be alleviated, effectively avoiding the premature breakdown of the devices. It is found that the acceptor concentration, thickness, width, and surface charge density of the incorporated JTE are closely associated with the electric field distribution and the reverse breakdown characteristics. The vertical SBDs with optimum p‐GaN JTE parameters feature a dramatic improvement in Baliga's figure of merit, without obvious degradation in the forward and dynamic performance. Selective p‐doping and acceptor activation is also demonstrated, which verifies the fabrication feasibility of the proposed JTE structures. Through the results, the way can be paved for the design and fabrication of high‐performance GaN vertical power devices toward high‐voltage, high‐power, and high‐speed applications.

Optimization of Two‐Zone Step‐Etched Junction Termination Structures for Vertical GaN Power Devices

One of the key elements of vertical high‐voltage GaN‐based devices is a properly designed junction termination extension (JTE) structure. One of the approaches to the fabrication of JTE structures is the use of p‐type epitaxial layers and their appropriate shaping to obtain high values of breakdown voltage. In this work, optimization of two‐zone (TZ) step‐etched JTE structures for vertical GaN power devices using technology computer aided design simulations is presented. Two constructions of the device are used, with a single‐zone (SZ‐JTE) and TZ‐JTE (TZ‐JTE) structure. The dependence of the breakdown voltage of SZ‐JTE structure is very sensitive to its thickness. The maximum breakdown voltage of 1654 V is obtained for the SZ‐JTE thickness of 110 nm. The use of a TZ‐JTE with an appropriate segment thickness ratio allows for a breakdown voltage above 75% of the theoretical value (≈1500 V) for a much wider range of JTE thicknesses and to achieve higher values of the breakdown voltage, reaching ≈96% of the theoretical value (1887 V). Finally, the performed simulations allow to map the full dependence on the thickness of the TZ‐JTE areas (2D‐map) and to determine the process window leading to the breakdown voltage above 1500 V.

Single-event burnout in homojunction GaN vertical PiN diodes with hybrid edge termination design

GaN devices play a major role in modern electronics, providing high-power handling, efficient high-frequency operation, and resilience in harsh environments. However, electric field crowding at the edge of the anode often limits its full potential, leading to single-event effects (SEEs) at lower bias voltages under heavy ion radiation. Here, we report on the performance of homojunction GaN vertical PiN diodes with a hybrid edge termination design under heavy ion irradiation, specifically, oxygen ions, chlorine ions, Cf-252 fission fragments, and alpha particles from an Am-241 source. The unique hybrid edge termination (HET) design provides better electric field management, preventing breakdown from occurring at the edge of the anode at lower voltages. The results of this study reveal that these devices exhibit excellent tolerance to 12-MeV oxygen and 16-MeV chlorine ions, owing to their low linear energy transfer (LET) and range in GaN. However, single-event burnout (SEB) is observed during the Cf-252 exposure at about 50% of the diodes' electrical breakdown voltage due to the presence of higher LET and longer-range ions. Optical and scanning electron microscopy (SEM) reveal that the damage that caused by SEB lies close to the center of these devices rather than the anode edge. Devices with junction termination extension (JTE) instead of HET edge termination also show similar SEB when irradiated with Cf-252 fission fragments. Physical damage due to SEB occurs at the edge of the anode for these devices. These comparative results show the benefits of HET for enhancing the resistance of GaN-based PiN diodes to heavy ion irradiation.

Optimization of Step-Etched Junction Termination Extensions for Vertical GaN Devices

Optimization of Step-Etched Junction Termination Extensions for Vertical GaN Devices

Prediction of JTE breakdown performance in SiC PiN diode radiation detectors using TCAD augmented machine learning

The design of Junction Termination Extension (JTE) is an important step for meeting the reliability requirement of SiC PiN diode radiation detectors. For early evaluation, Technology Computer Aided Design (TCAD) software is often used to simulate the electronic property of detectors with different JTE parameters. But it is time consuming, which need 1 h or even longer for one case. Here, a TCAD augmented Machine Learning (ML) method based on the fully connected Neural Network (NN) algorithm is proposed to predict the breakdown performance quickly with different parameters of Spatial Modulation (SM) JTE. Utilized ∼5000 datum generated by TCAD simulation, the ML model could be established and achieve good prediction of breakdown voltage and location within a few seconds. As a semi-supervised learning model, its prediction accuracy of breakdown location is higher than 89.4 % and the determination coefficient R2 of breakdown voltage could be up to 0.97 compared with TCAD simulations. Moreover, this model could give the relationship curve of breakdown voltages and doping concentration, which is useful to choose an ideal structure with a wide implantation dose window. Based on this ML prediction model, the design cycle of SiC PiN diode radiation detectors could be reduced significantly.

Multiple P-Type SiC Micro-Island as Junction Termination Extension for 4H-SiC Schottky Barrier Diode

Multiple P-Type SiC Micro-Island as Junction Termination Extension for 4H-SiC Schottky Barrier Diode

Analysis of Basal Plane Dislocation Motion Induced By P+ Ion Implantation Using Synchrotron X-Ray Topography

Silicon Carbide (SiC) is a promising wide bandgap semiconductor for future power devices since it has a wide bandgap, high breakdown voltage and good thermal stability [1]. The most mature method to perform selective area doping in 4H-SiC epiwafers during fabrication is ion implantation [2]. However, such implantation processes employing high energy ions can damage the lattice in the epilayers that can subsequently lead to formation and migration of basal plane dislocations (BPDs) which are known to be detrimental to the performance of the devices [3-4]. Implantation processes are typically conducted under room temperature (RT) conditions, but high temperature (HT) implantation is favorable when the dose level is high [5]. Oxide layer for blocking purpose is inevitable since photoresist can barely remain intact under such high temperature, which will increase the time, cost, and complexity [6-7].Here, we will primarily emphasize the motion of the BPDs under stress from RT implantation. 1.2 kV-rated 4H-SiC PiN diodes with junction termination extension (JTE) annealed with same conditions have been successfully fabricated by implantation with different dose levels and concentration profiles under room temperature and at 600 ˚C. Concentration profiles simulated by Stopping and Range of Ions in Matter (SRIM) are shown in Fig.1(a) [8]. The JTEs were implanted with lower concentrations. Synchrotron monochromatic beam X-ray topography (SMBXT) has been performed to characterize the defects induced by implantation and annealing process. Topographs of PIN diodes are shown in Fig.1 (b)-(h). For the diodes implanted with 1x under RT and HT, there is no evidence of dislocations generated due to implantation and annealing. However, formation of BPD half loops, as highlighted in the red and yellow boxes, can be observed from the edge of the device when the dose level is elevated to 5x and 9x. In addition to that, the basal plane density (BPD) density of 5x RT Box due to implantation and annealing is much more significant than that of 5x RT and 9x RT, indicating that concentration profile can affect the defect generation. Fig.1 (e) shows topograph of PiN diode implanted with 5x under high temperature. The absence of BPDs compared to the RT implanted device to the same concentration profile suggests the generation of BPD is suppressed by the high temperature condition. In 5x RT Box device, opposite sign BPDs are nucleated from opposite edges of device, as indicated in Fig.1 (f)&(g). Here, we will analyze the motion of dislocations generated by ion implantation and annealing.Reference:[1] J. Guo, Y. Yang, B. Raghothamachar, T. Kim, M. Dudley, J. Kim, J. Cryst. Growth[2] F. Roccaforte, P. Fiorenza, M. Vivona, G. Greco, F. Giannazzo, Materials 14(14) (2021) 3923.[3] K. Konishi, R. Fujita, Y. Mori and A. Shima, Semiconductor Science and Technology 2018 Vol. 33 Issue 12[4] M. Nagano, H. Tsuchida, T. Suzuki T. Hatakeyama, J. Senzaki and K. Fukuda, J. Appl. Phys. 108, 013511 (2010)[5] S. Mancini, S. Y. Jang, Z. Chen, D. Kim, Y. Liu, B. Raghothamachar, M. Kang, A. Agarwal, N. Mahadik, R. Stahlbush, M. Dudley, W. Sung, proceeding of 2022 IEEE International Reliability Physics Symposium (IRPS). (accepted)[6] T. Kimoto, J. A. Cooper. John Wiley & Sons Singapore Pte. Ltd. 2014. pp. 197-200[7] D. Kim, N. Yun and W. Sung, 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405109[8] J. F. Ziegler, M.D. Ziegler, J.P. Biersack, Nucl Instrum Methods Phys Res B, Volume 268, Issues 11–12, June 2010, Pages 1818-1823 Figure 1

(Invited) Recent Progress in Medium-Voltage Vertical GaN Power Devices

Vertical gallium nitride (GaN) power devices continue to garner interest in multiple power conversion applications requiring a medium-voltage (1.2 – 20 kV) capability. Currently, silicon carbide (SiC) is addressing this voltage range, however, with a comparable critical electric field and superior mobility, GaN is expected to offer advantages in applications where fast switching and avalanche breakdown response times are desired. While uses in electric vehicles, solid-state transformers, and renewable energy conversion are being actively explored, the potential of a vertical GaN device for electric grid protection in the form of an electromagnetic pulse arrestor is a unique proposition that requires very fast transient capabilities (<1 µs pulse widths with rise-times on the order of 10 ns). However, vertical GaN devices are significantly less mature than present SiC offerings. Specifically, low-doped, thick epitaxial growth of GaN via metal-organic chemical vapor deposition (MOCVD) still presents many challenges, and advancements in processing, manufacturability, and failure analysis are needed.In this work, we describe our efforts to address the above issues and advance the state-of-the-art in vertical GaN PN diode development. We have successfully demonstrated an MOCVD-grown, 50 µm thick, low-doped (<1015 cm-3) drift region on a GaN substrate that was processed into relatively large-area (1 mm2) PN diodes capable of achieving a 6.7 kV breakdown. Temperature-dependent breakdown was observed, consistent with the avalanche process. The devices consisted of a 4-zone step-etched junction termination extension (JTE), where the breakdown region was visualized via electroluminescence (EL) imaging. Ongoing work aims to scale the current capability of the medium-voltage diodes through a parallel interconnect design that negates defective or poor performing diodes. Further investigation of edge termination structures was explored using a bevel approach, where we studied the relationship between the bevel angle and p-doping. It was found that a very shallow angle of only 5° accompanied by a 500 nm p-region consisting of 3×1017 cm-3 Mg concentration resulted in a consistent 1.2 kV breakdown for an 8 µm thick, 1.6×1016 cm-3 doped drift region. EL imaging confirmed uniform breakdown, and temperature dependence was demonstrated. The bevel approach was then implemented on a diode structure with a 20 µm thick drift region capable of 3.3 kV breakdown, where an unclamped inductive switching (UIS) test was performed to evaluate the impact of a field plate design on avalanche uniformity and ruggedness.A parallel effort to establish a foundry process for vertical GaN devices has been underway. Initially, this focus was on comprehensive studies of GaN wafer metrology using capacitance-voltage (C-V) mapping, optical profilometry, and x-ray diffraction (XRD) mapping. A machine learning algorithm was implemented to identify defective regions and produce a yield prediction for each GaN wafer prior to processing. A hybrid edge termination structure consisting of implanted guard rings (GR) and JTEs was developed in coordination with a controlled experiment that varied the anode thickness, and therefore the remaining p-GaN after implantation. It was observed that thinner p-GaN regions under the JTE/GR region resulted in a significant (>100x) reduction in leakage current under reverse-bias conditions. This process has resulted in 1.2-kV-class devices with up to 18 A forward current for a 1 mm2 device with a specific on-resistance of 1.2 mOhm-cm2. The foundry effort has since been extended to 3.3-kV-class devices that utilize 25 µm thick drift layers with ~2-4×1015 cm-3 doping. These devices have demonstrated up to 3.8 kV breakdown with leakage currents <1 nA up to 3 kV. More than 40 wafers have been processed to date, resulting in >20,000 devices. Statistical variations in I-V and C-V characteristics will be discussed. Packaging process development and analysis are underway to develop electrical stress procedures and identify fundamental failure mechanisms. Finally, a pulse arrested spark discharge (PASD) setup, capable of up to 15 kV pulsed operation in 100 V steps, was implemented to quantify the time response of avalanche breakdown. Initial results on a packaged 800 V device showed a ~1 ns response time during breakdown, which reinforces the potential EMP grid protection applicability. This work was supported by the ARPA-E OPEN+ Kilovolt Devices Cohort directed by Dr.Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy of the United States Government.

(Invited) Advanced Design Concepts for Vertical Gallium Nitride MOSFETs

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. Gallium nitride (GaN) is of interest for vertical device architectures but directly competes with the already established silicon carbide (SiC) power devices. In the case of vertical GaN rectifiers which are unipolar figure-of-merit limited, the materials advantage of GaN provides a modest gain in terms of critical electric field and very slight gains in bulk mobility and saturation velocity, while being at a disadvantage in terms of thermal conductivity compared to SiC. However, despite still being a very immature technology, vertical GaN MOSFETs have demonstrated channel mobilities upwards of 200 cm2/V·s, over three times that of SiC-based MOSFETs. For 1200V-class devices, channel mobility directly contributes to a significant portion of device on-resistance, and it is therefore expected that vertical GaN MOSFETs would offer a substantial performance advantage compared to SiC MOSFETs. Despite this, the development of vertical GaN devices that demonstrate this theoretical potential faces many challenges. Several fundamental limitations exist within the manufacturing process that prohibit GaN devices from directly mirroring the design rules for similar SiC devices. In this talk, we will discuss several key design concepts recently developed for vertical GaN MOSFETs which serve to address several critical issues for GaN.Limitations in selective-area doping for GaN provide an additional challenge in designing edge termination structures, advanced features that protect the gate dielectric during the blocking state, and provides restrictions on minimizing cell pitch. Proper edge termination design is required to reach an avalanche voltage near the theoretical limit and avoid early breakdown. We present an optimized design point for the edge termination with a good match between theoretical and experimental data using a step-etched junction termination extension. Despite a well-designed edge termination, early breakdown will occur in the gate dielectric at the bottom of the gate trench due to field crowding in the dielectric at high blocking voltages. We propose a new method for protecting the gate dielectric by means of a buried field shield formed by an etch-and-regrowth process. Experimental data shows this gate dielectric failure can occur as early as 1/3rd of the designed blocking voltage. The field shield design is shown in simulation to sufficiently reduce the electric field in the gate dielectric to below 4 MV/cm with minimal or no derating of the device depending on geometry of the shield. Additional methods will be presented on new techniques to minimize cell pitch, a critical factor necessary to compete against SiC. Cell pitch minimization not only reduces on-resistance and gate-charge trade-offs, but it is also a driving factor to reduce cost and increase die density on wafer. Finally, techniques have been developed for advanced metal contact designs specific to the trench MOSFET, which further aid in reducing cell pitch. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

1.7-kV vertical GaN p-n diode with triple-zone graded junction termination extension formed by ion-implantation

Edge termination has emerged as an important area in the design and realization of vertical GaN power electronic devices. While the material properties of GaN are promising for high-performance devices, in practice the breakdown voltage can be compromised by inadequate edge termination (ET). While solutions in other materials (e.g. Si, SiC) are well-known, these are challenging to implement in GaN due to inherent difficulties in p-type doping GaN. In this work, we report a etch-free triple-zone graded junction termination extension (JTE) for vertical GaN diodes formed by Nitrogen ion implantation. The triple-zone design offers lower peak fields for effective field control. In addition, the proposed triple-zone JTE is beneficial for increasing the fabrication process window and allowing for more variability in epitaxial wafer growth in terms of p-GaN doping and thickness while maintaining high breakdown voltage. The fabricated GaN p-n diodes with triple-zone JTE obtain a maximum breakdown voltage of 1.73 kV with specific on-resistance Ron of 0.4 mΩcm2. Temperature-dependent reverse characteristics show that the devices have a positive temperature coefficient of the breakdown voltage indicating an avalanche breakdown mechanism. These results suggest that vertical GaN p–n diodes with N-implanted triple-zone JTE are promising for power applications.

Electrical Properties of Ga2O3 Schottky Barrier Diodes with and without Mesa Structure

Devices based on wide bandgap (WBG) semiconductors like silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) are ideal for high-power electronics in harsh environments. Among the WBG semiconductors, ultrawide bandgap (UWBG) β-phase gallium oxide (Ga2O3), EG ≈ 4.8 eV, is emerging as a replacement for the current commercially available wide bandgap (WBG) power electronics due to its generational improvements in performance and manufacturing cost [1]. Ga2O3 has a high theoretical breakdown electrical field of 8 MV/cm which in turn gives its Baliga’s figure of merit for power devices that is larger than other WBG materials. The availability of high-quality Ga2O3 substrates produced from melt-grown bulk single crystals also facilitates the development of vertical power devices.In the current stage, the vertical Schottky barrier diode (SBD) with Ga2O3 can have an improved current spreading effect when compared to power diode devices from Si, SiC, and GaN. Especially, the Ga2O3 is expected to surpass the trade-off relationship between breakdown voltage (BV) and on resistance (Ron,sp) that other materials have [2]. Nevertheless, the Ga2O3 vertical SBD still cannot achieve the theoretical breakdown electric field. One of the key topics for WBG semiconductors application is a structure for improved electrical management such as field rings, junction termination extension, and field plates to reduce the leakage current in the reverse bias state.Here, we investigate the characteristics of Ga2O3 SBDs with and without mesa structure in extreme environments at high and low temperature. Conventional and mesa Ga2O3 SBDs were fabricated on the halide vapor phase epitaxy (HVPE) grown β-Ga2O3 (001). A Sn-doped substrate with 61016 cm-3 was used for the HVPE growth. In the SBD with mesa structure, the circular mesa with a diameter of 162 μm and a depth of 500 nm was formed around anode electrodes. The Ti/Au metal stack on the back side of the substrate acted as a cathode and the anode electrode deposited Ni/Au/Pt layers. After the fabrication process, current-voltage (I-V) measurements were performed on the SBDs between -5 V and 1 V. From the results, the values of Ron,sp at 0.7 V are 46.4 Ω•cm2 and 46.2 Ω•cm2 in conventional and mesa SBDs, respectively. And additionally, the leakage current at -5 V is reduced by approximately 44.3% in the mesa structure. To obtain the Schottky barrier height (SBH) from I-V and capacitance-voltage (C-V) measurements, the C-V was observed in the range of -5 V to 0.5 V at 100 kHz. The SBH values from I-V and C-V measurements, the mesa SBDs have 1% - 5% larger SBH compared to the conventional structure, and it could be related to lower leakage current. Moreover, the depletion depths of conventional and mesa SBDs were 52.2 nm and 57.8 nm, respectively, from C-V measurements. For considering the electrical characteristics in extreme temperatures, the I-V measurements of both SBDs structure will be measured between 75 K to 525 K. From an initial low temperature measurement series, we determine a Richardson constant of 49 A/cm2 comparable to what has been reported by other groups. Furthermore, we will extend the study by performing deep-level transient spectroscopy (DLTS) to understand the defect information in Ga2O3.

Vertical Diamond p-n Junction Diode with Step Edge Termination Structure Designed by Simulation.

In this paper, diamond-based vertical p-n junction diodes with step edge termination are investigated using a Silvaco simulation (Version 5.0.10.R). Compared with the conventional p-n junction diode without termination, the step edge termination shows weak influences on the forward characteristics and helps to suppress the electric field crowding. However, the breakdown voltage of the diode with simple step edge termination is still lower than that of the ideal parallel-plane one. To further enhance the breakdown voltage, we combine a p-n junction-based junction termination extension on the step edge termination. After optimizing the structure parameters of the device, the depletion regions formed by the junction termination extension overlap with that of the p-n junction on the top mesa, resulting in a more uniform electric field distribution and higher device performance.

2.83-kV double-layered NiO/β-Ga2O3 vertical p-n heterojunction diode with a power figure-of-merit of 5.98 GW/cm2

This work demonstrates high-performance NiO/β-Ga2O3 vertical heterojunction diodes (HJDs) with double-layer junction termination extension (DL-JTE) consisting of two p-typed NiO layers with varied lengths. The bottom 60-nm p-NiO layer fully covers the β-Ga2O3 wafer, while the geometry of the upper 60-nm p-NiO layer is 10 μm larger than the square anode electrode. Compared with a single-layer JTE, the electric field concentration is inhibited by double-layer JTE structure effectively, resulting in the breakdown voltage being improved from 2020 to 2830 V. Moreover, double p-typed NiO layers allow more holes into the Ga2O3 drift layer to reduce drift resistance. The specific on-resistance is reduced from 1.93 to 1.34 mΩ·cm2. The device with DL-JTE shows a power figure-of-merit (PFOM) of 5.98 GW/cm2, which is 2.8 times larger than that of the conventional single-layer JTE structure. These results indicate that the double-layer JTE structure provides a viable way of fabricating high-performance Ga2O3 HJDs.