(Invited) Advanced Design Concepts for Vertical Gallium Nitride MOSFETs

Abstract

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. Gallium nitride (GaN) is of interest for vertical device architectures but directly competes with the already established silicon carbide (SiC) power devices. In the case of vertical GaN rectifiers which are unipolar figure-of-merit limited, the materials advantage of GaN provides a modest gain in terms of critical electric field and very slight gains in bulk mobility and saturation velocity, while being at a disadvantage in terms of thermal conductivity compared to SiC. However, despite still being a very immature technology, vertical GaN MOSFETs have demonstrated channel mobilities upwards of 200 cm2/V·s, over three times that of SiC-based MOSFETs. For 1200V-class devices, channel mobility directly contributes to a significant portion of device on-resistance, and it is therefore expected that vertical GaN MOSFETs would offer a substantial performance advantage compared to SiC MOSFETs. Despite this, the development of vertical GaN devices that demonstrate this theoretical potential faces many challenges. Several fundamental limitations exist within the manufacturing process that prohibit GaN devices from directly mirroring the design rules for similar SiC devices. In this talk, we will discuss several key design concepts recently developed for vertical GaN MOSFETs which serve to address several critical issues for GaN.Limitations in selective-area doping for GaN provide an additional challenge in designing edge termination structures, advanced features that protect the gate dielectric during the blocking state, and provides restrictions on minimizing cell pitch. Proper edge termination design is required to reach an avalanche voltage near the theoretical limit and avoid early breakdown. We present an optimized design point for the edge termination with a good match between theoretical and experimental data using a step-etched junction termination extension. Despite a well-designed edge termination, early breakdown will occur in the gate dielectric at the bottom of the gate trench due to field crowding in the dielectric at high blocking voltages. We propose a new method for protecting the gate dielectric by means of a buried field shield formed by an etch-and-regrowth process. Experimental data shows this gate dielectric failure can occur as early as 1/3rd of the designed blocking voltage. The field shield design is shown in simulation to sufficiently reduce the electric field in the gate dielectric to below 4 MV/cm with minimal or no derating of the device depending on geometry of the shield. Additional methods will be presented on new techniques to minimize cell pitch, a critical factor necessary to compete against SiC. Cell pitch minimization not only reduces on-resistance and gate-charge trade-offs, but it is also a driving factor to reduce cost and increase die density on wafer. Finally, techniques have been developed for advanced metal contact designs specific to the trench MOSFET, which further aid in reducing cell pitch. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.