Junction Technology Research Articles

Three-mask polycrystalline silicon TFT with metallic gate and junctions

Polycrystalline silicon thin-film transistors (TFTs) with metallic gates and junctions realized using a three-mask metal-replaced junction (MERJ) technology have been fabricated and characterized. Compared to those of a conventional TFT, the process of making a MERJ TFT is simplified, and the resistance of the junctions and gate is reduced. The low resistance of the metallic junctions allows a greater recovery of the intrinsic characteristics of a MERJ TFT, and the reduced signal delay on a low-resistance metallic gate line makes the TFT particularly suitable for realizing large-area active-matrix flat-panel displays.

Performance study of radiation detectors based on semi-insulating GaAs with P+ homo- and heterojunction blocking electrode

Abstract A preliminary study of technology and performance of radiation detectors based on bulk semi-insulating (SI) GaAs with P+ blocking electrodes is presented. Detectors with blocking electrode system formed either by P+(GaAs)/N–(SI GaAs) homojunction or P+(Al0.3Ga0.7As)/N–(SI GaAs) heterojunction are prepared. Room-temperature I–V characteristics, measurement and evaluation of pulse–height spectra using 241Am and 57Co radionuclide sources were performed for the characterization of the fabricated detectors. The aim of the study is to verify the possibility to improve the performances of SI GaAs radiation detectors based on the Schottky contact by using the more sophisticated P+–N junction technology. The obtained results and the possibility of future improvements of SI GaAs radiation detectors to be used in digital X-ray imaging are discussed.

Normal metal–insulator–superconductor junction technology for bolometers

Normal metal–insulator–superconductor tunnel junctions are candidates for large-format arrays of ultra-low noise equivalent power bolometers. Using a wafer scale process we have fabricated devices with the required sub μ m 3 volumes and ohmic superconductor–normal metal contacts for delivering power loads. Additionally, we demonstrate simultaneous tunnel junction thermometry and SQUID-based Johnson current noise thermometry.

High-Temperature Operation of Oxide SFQ-Circuit-Elements

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.

Roughness of amorphous/crystalline interface in pre-amorphization implantation: Molecular dynamic simulation and modeling

Pre-amorphization implantation has been applied as a shallow junction technology. Roughness at amorphous/crystalline (a/c) interface should be controlled to improve junction characteristics. To understand and model a/c interface roughness, molecular dynamic method is applied in simulating pre-amorphization implantation. A method to reproduce roughness at a/c interface by molecular dynamic simulation is presented. A model of interface roughness is presented. Si and Ge implantation from 2–20 keV at a dose of 1 × 10 15 cm −2 is simulated. The depth of a/c interface is reproduced. Experimental results of a/c interface roughness are successfully simulated. The interface roughness is well reproduced and interpreted by the model presented.

Quantitative Evaluation of the Single-Flux- Quantum Cross/Bar Switch

We demonstrated the 4 /spl times/ 4-cross/bar-40 Gbps/ch switch which is functionally compatible with a commercial semiconductor one in order to evaluate the current SFQ circuit technology quantitatively in both a operating speed and power consumption. According to our numerical simulations, the SFQ switch has one or two orders of magnitude higher throughput per a single channel than that of the semiconductor, and has much smaller exchanging times between routing paths. In an actual test based on the NEC Nb-2.5 kA/cm/sup 2/ junction technology, correct operation using an on-chip test system made up of 4700 Josephson junctions was confirmed up to 37 Gbps/ch which is about 14 times faster than the semiconductor of 2.7 Gbps/ch speed. We also confirmed that SFQ circuits consumed 1/800 power compared with those of semiconductor. The reason why data rates obtained experimentally did not reach the designed speed of 40 Gbps/ch is due to both the timing error and the influence of magnetic fields caused by large bias currents exceeding 500 mA. These results of quantitative evaluation show that the SFQ technology has much greater potentials than the semiconductor one in both the operating speed and the power consumption, which means it is very effective to apply the SFQ technology to digital applications.

Practical High-Resolution Programmable Josephson Voltage Standards Using Double- and Triple- Stacked<tex>$rm MoSi_2$</tex>-Barrier Junctions

We have developed vertically stacked superconductor normal-metal-superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double- and triple- stacked MoSi/sub 2/ barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm /spl times/ 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

Fabrication of<tex>$a/c$</tex>Axes Oriented Grain Boundaries in YBCO Films by Selective Growth

The a/c axes grain boundaries of YBCO films are very interesting from the viewpoints of Josephson junction technology and the magnetic flux pinning. In this paper, we intend to flow superconducting current along the grain boundary and to prevent the magnetic flux motion from passing across the grain boundary. The a/c axes grain boundaries were fabricated on SrLaGaO/sub 4/ (100) substrates by pulsed laser deposition on Gd/sub 2/CuO/sub 4/ (GCO) buffer layers. The preferred orientation and in-plane orientation of the films were characterized by X-ray /spl theta//2/spl theta/ diffraction and /spl phi/-scan spectroscopy. 4-micrometer pitch GCO patterns were fabricated by a lithography technology. Subsequently, the YBCO films were deposited on the pattern. A TEM image showed that a-axis grains grew over c-axis grains.

Superconducting Quantum Interference Filters Operated in Commercial Miniature Cryocoolers

Superconducting Quantum Interference Filters (SQIF's) are multi-loop arrays of Josephson junctions possessing unconventional grating structures. The flux-to-voltage transfer function of SQIF's is unique and has a single delta-peak like characteristics at zero applied magnetic field. The fault tolerance of SQIF's allows them to be realized in standard high-temperature grain boundary Josephson junction technology. We have successfully designed high-temperature YBCO SQIF's with voltage swings of more than 3 mV and a rather large dynamical range. This large dynamical range allows high-Tc SQIF's to be operated in commercial miniature cryocoolers at 50 K-80 K without any significant problems. Typical parasitic oscillations which are induced by the 55 Hz driven compressor of the cryocooler do not degrade the performance of SQIF's. Even if SQIF's are operated fully unshielded no significant degradation of the performance has been observed.

Double Relaxation Oscillation SQUID with a 4JL On-Chip Digital Flux Locked-Loop Circuit

Double relaxation oscillation SQUID (DROS) combined with an on-chip superconducting digital flux locked-loop (FLL) circuit has been proposed. In this study, we described superconducting digital FLL circuit which consists of an 8-bit up/down counter and an 8-bit R-2R ladder D/A converter. The circuit was designed using 4-Junction Logic (4JL)-gates which are driven by a two phase power supply. In the up/down counter, we employed binary carry lookahead (BCL) circuits for high-speed operation. Logic simulations for the BCL 8-bit up/down counter showed correct operation up to 4 GHz, assuming a 2.5 kA/cm/sup 2/ Nb/Al-AlO/sub x//Nb junction technology. From simulation results high slew rate of 10/sup 7//spl Phi//sub 0//s and dynamic range of 2.5/spl Phi//sub 0/ can be expected.

Demonstration of the Multi-Bit Sigma-Delta A/D Converter With the Decimation Filter

We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.

2.6-V High-Resolution Programmable Josephson Voltage Standard Circuits Using Double-Stacked MoSi<tex>$_2$</tex>-Barrier Junctions

Using a new circuit design and double-stacked junction technology we have demonstrated fully functional high-resolution programmable voltage standard chips with 67 410 junctions that operate up to a maximum output voltage of 2.6 V. The circuit uses double-stacked junctions, where two junctions are fabricated in each stack, in order to increase the output voltage. We have also improved the voltage resolution at fixed frequencies 16-fold by using a circuit optimized for three voltage states and 128-fold below 2 V by oppositely biasing two large arrays whose junction counts differ by a single stack. These circuits operate over a frequency range from 14 GHz to 19 GHz with a 2-mA maximum operating current range.

New type of SFQ-dc converter for use in oxide circuits

An SFQ-dc converter has been designed and fabricated for use in oxide RSFQ circuits. The SFQ-dc converter comprised a stack of SQUIDs, Josephson transmission line (JTL) for a set signal, and current-injection line for a reset signal. The SFQ-dc converter of this type was found to have wide operation region with respect to the junction critical current. The SFQ-dc converter was fabricated by the ramp-edge junction technology and could be successfully operated with the output voltage as much as 0.5 mV.

Insulators for YBa2Cu3O7Josephson Junction Technology

Insulators for YBa₂Cu₃O₇Josephson Junction Technology

環境・エネルギー問題と膜 混合伝導体を用いた腹式反応器によるメタンからの合成ガス製造−ＪＲＣＭプロジェクトにおける研究成果−

Teikoku Oil Co., Ltd. is carrying out the new technical development which manufactures synthetic gas or hydrogen efficiently using the oxygen transmission ceramics membrane which has mixed conductivity. Development of the membrane reactor using the mixed conductor which unified the oxygen separation and methane partial oxidization reaction are expected as a new device of the synthetic gas manufacture technology from a natural gas.Until now, optimization of a mixed conductor and catalyst material, the catalyst arrangement method in a membrane reactor, structure, seal junction technology, a simulation, etc. are carried out to reporting the knowledge from which many results were raised in the category called component engineering. Although self supported membrane attained oxygen flux 20 cc/min/cm2, supported membrane attained oxygen flux 13 cc/min/cm2 in this study.Membrane material with higher stability are developed, next step is to shift to construction of the actual pilot plant of an oxygen membrane ATR reactor.

Controlled-junction superconducting quantum interference device via phonon injection

The direct current superconducting quantum interference device (DC-SQUID), using controlled Josephson junction technology, provides a mechanism to modify the characteristics of the device post-fabrication. We report on the fabrication and measurement of a micron sized DC-SQUID using two Dayem bridge weak-link Josephson junctions with integrated “heaters.” The weak link critical current is controlled by hot phonons from the current biased titanium, normal metal heater. By using the heaters, control over the critical current oscillations of the SQUID was observed at 4.2K.

On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.

Hot phonon controlled-junction superconducting quantum interference device

The optimal design of a direct current superconducting quantum interference device (DC-SQUID) with high sensitivity requires two identical Josephson junctions, which is difficult to achieve. The design of a DC-SQUID using controlled Josephson junction technology provides a mechanism for modifying the characteristics of the device. Here we report on the nano-fabrication and measurement of a DC-SQUID utilizing two Dayem bridge weak-link Josephson junctions fabricated with a width ∼100 nm and a length of ∼200 nm. These junctions are controlled via the irradiation of hot phonons from nearby titanium/chromium normal metal constrictions which are current biased. The devices were measured at a temperature of 4.2 K and control over the critical current oscillations was observed.

Design of single-flux-quantum universal gates with a wide operating margin

We have successfully designed single-flux-quantum (SFQ) universal gates with a wide operating margin. We have previously presented universal gates such as NAND and NOR gates. These universal gates have a small operating margin and should be optimized to realize a wide operating margin. In this study, we newly designed universal gates and optimized the device parameters using an SFQ circuit-optimizing tool. Assuming a 1 kA cm−2 Nb/Al–AlOx/Nb junction technology, the newly designed NAND and NOR gates had a critical margin of more than ±20% for 20 GHz operation. Direct-current bias margins for NAND and NOR gates were also exceeded by ±30% for 20 GHz operation.

Phase-locking in a nonuniform array of tunnel junctions

A nonuniform, one-dimensional tunnel junction array that is designed to promote phase-locking to an ac pump signal is proposed and theoretically investigated for possible information processing applications. The tunnel resistances of the junctions in one part of the array are tailored to provide phase restoration for electrons tunneling in the array, while the tunnel resistances in the other part of the array are designed to provide a time delay with minimal jitter. It is shown that phase-locking of the tunneling is possible at the fundamental and at the one-half subharmonic of the pump frequency. While the required parameter ranges and the necessary degree of control of this design are not practical for tunneling phase logic based on conventional tunnel junction technologies, the proposed design could potentially be realized in a molecular system.