Junction Field Effect Transistor Research Articles

Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part II: Total Charges and Transcapacitances

A compact model for the dynamic operation of double-gate junction field-effect transistors is established in this paper. Analytical model expressions are developed for the total node charges and transcapacitances valid from subthreshold to above threshold and from linear to saturation operation. The model is shown to conserve symmetry among source and drain, and circumvents problems at zero drain-to-source bias.

CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications.

In this work, we present a CMOS-integrated low-noise junction field-effect transistor (JFET) developed in a standard 0.18 pm CMOS process. These JFETs reduce input-referred flicker noise power by more than a factor of 10 when compared to equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input, significant for many applications in bioelectronics.

Static and Dynamic Characterization of a 3.3 Kv, 45 A 4H-Sic MOSFET

Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.

Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

Cross-Section Doping Topography of 4H-SiC VJFETs by Various Techniques

Different methods for cross-section characterization of SiC Trenched-singly-implanted vertical junction field effect transistors (TSI-VJFETs) are presented with the purpose to determine the epitaxial structure in terms of doping topography.

Normally-off AlGaN/GaN heterostructure junction field-effect transistors with blocking layers

In this study, normally-off AlGaN/GaN heterostructure junction field-effect transistors (HJFETs) with p-GaN cap layer were reported, in which intrinsic GaN were proposed as blocking layers between the p-GaN cap layer and the AlGaN layer to alleviate the Mg diffusion. It demonstrates that the p-GaN gated devices present negative shift in the threshold voltage but larger output current density with the increasing thickness of the blocking layer. We found that a 20 nm blocking layer can efficiently block the Mg diffusion into the AlGaN/GaN heterostructure and a channel mobility of 1200 cm2V−1s−1 was obtained. This value is comparable to the result obtained from a conventional AlGaN/GaN heterostructure, which means that the p-GaN cap shows no obvious degradation on channel mobility owing to the introduction of the blocking layer. The electrical performance of the recess region (without p-GaN cap) also confirm the channel degradation which can mainly ascribed to the Mg diffusion.

Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

High-Temperature Operation of n- and p-Channel JFETs Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate

Silicon carbide (SiC) n-channel and p-channel junction field-effect transistors (JFETs) were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate toward complementary-JFET integrated circuit applications under a harsh environment. The fabricated n-JFET and p-JFET on a common substrate without an epitaxial layer show normal transistor operations up to 400 °C. Their electrical characteristics are comparable with theoretical estimations obtained from material parameters of n- and p-type SiC epitaxial layers. The present results assure that not only JFETs but also a variety of devices can be made by direct ion implantation while keeping material properties of epitaxially grown SiC.

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

Quasi-Two-Dimensional β-Ga2O3 based Hetero-Structure Transistors

β-Ga2O3 is a wide band gap (4.8 eV) semiconducting material with outstanding chemical and thermal stabilities. As the breakdown voltage of β-Ga2O3 is estimated to be as high as 8 MV/cm, it can be applied to high-power electronics. After β-Ga2O3 thin layers were successfully exfoliated from bulk single crystals by mechanical exfoliation method, the study of high power 2D nano-electronics using β-Ga2O3 received a considerable attention. Though β-Ga2O3 is not a two-dimensional Van der Waals material like graphene and MoS2, a bulk β-Ga2O3 crystal can be easily cleaved into thin nano-flakes in the (100) direction; it has monoclinic structure and the lattice constant is larger along the cleaved plane. Moreover, this ultrathin β-Ga2O3 flakes can be integrated with other 2D materials such as hexagonal boron nitride (h-BN) and transition metal dichalcogenides (TMDs) to make down-scaled, flexible devices. We demonstrated two types of heterostructure devices (MISFETs and JFETs) based on β-Ga2O3 flakes and 2D materials using PDMS stamp method and photolithography. β-Ga2O3/h-BN hetero-structure based quasi-two-dimensional metal insulator semiconductor field-effect transistors(MISFETs) are fabricated. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities at the interface between β-Ga2O3 and h-BN, resulting in excellent device performances. The fabricated MISFETs showed superior drain current modulation with high on/off ratio and low gate leakage current. The double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. N-channel β-Ga2O3/WSe2 heterostructure junction field effect transistors (JFETs) are demonstrated with good gate modulation and negligible hysteresis. Tungsten diselenide (WSe2) is mostly known as a stable p-type 2D layered material. The fabricated heterostructure JFETs also showed excellent ambient stability. The successful JFET operation is attributed to Van der Waals junction interface between β-Ga2O3 and WSe2. These heterostructured wide-band-gap nanodevices show a new route toward stable and high-power nanoelectronic devices. The details of the fabrication procedure and results will be presented.

Electrical Properties of Silicon Doped GaN Activated By Ion Implantation

One major goal of GaN based technology studies is the fabrication of rugged power switching devices. While this is best achieved through vertical GaN technology, the process development of GaN substrates is not yet mature, and the substrates for lateral power switch are more cost effect than GaN. A common way of doping lateral GaN devices is through ion implantation followed by rapid thermal annealing for ion activation. Activation of most p-type dopants requires temperatures above 1300 °C; however, silicon will activate as an n-type dopant at lower temperatures. This research reports on the electrical properties of devices such as junction field effect transistors and Van der Pauw structures containing silicon doped GaN activated by ion implantation.

Electrical characterization of the temperature dependence in CdTe/CdS heterojunctions deposited in-situ by pulsed laser deposition

The I-V and C-V characteristics of CdTe/CdS heterojunctions deposited in-situ by Pulsed Laser Deposition (PLD) were evaluated. In-situ deposition enables the study of the CdTe/CdS interface by avoiding potential impurities at the surface and interface as a consequence of exposure to air. The I-V and C-V characteristics of the resulting junctions were obtained at different temperatures, ranging from room temperature to 150 °C, where the saturation current (from 10−8 to 10−4 A/cm2), ideality factor (between 1 and 2), series resistance (from 102 to 105 Ω), built-in potential (0.66–0.7 V), rectification factor (∼106), and carrier concentration (∼1016 cm−3) were obtained. The current–voltage temperature dependence study indicates that thermionic emission is the main transport mechanism at the CdTe/CdS interface. This study also demonstrated that the built-in potential (Vbi) calculated using a thermionic emission model is more accurate than that calculated using C-V extrapolation since C-V plots showed a Vbi shift as a function of frequency. Although CdTe/CdS is widely used for photovoltaic applications, the parameters evaluated in this work indicate that CdTe/CdS heterojunctions could be used as rectifying diodes and junction field effect transistors (JFETs). JFETs require a low PN diode saturation current, as demonstrated for the CdTe/CdS junction studied here.

Improved device characteristics obtained in 4H-SiC MOSFET using high-k dielectric stack with ultrathin SiO2-AlN as interfacial layers

A novel method of stacking dielectric layers on top of Silicon carbide (SiC) is proposed to address the most common Silicon dioxide (SiO2)-SiC interface issues in SiC based metal oxide semiconductor (MOS) devices. Aluminum nitride (AlN) as an interfacial layer, instead of SiO2, between hafnium oxide (HfO2) and SiC showed improved device characteristics. However, incorporating SiO2 along with AlN as an interfacial layer is found to be the best way of stacking dielectric layers. This is concluded, based on the changes observed in the electrical characteristics of the device by intentionally varying lattice temperature (T), interface trap density (Dit) and junction field effect transistor (JFET) width. All the investigations are done in 4H-SiC half-cell planar n-channel MOS field effect transistor (MOSFET) using commercially available technology computer aided design (TCAD) software sentaurus device. Theoretical calculations show good agreement with the simulated results, and are compared with the published results.

NV-TCAM: Alternative designs with NVM devices

TCAM (ternary content addressable memory) is a special memory type that can compare input search data with stored data, and return location (sometime, the associated content) of matched data. TCAM is widely used in microprocessor designs as well as communication chip, e.g., IP-routing. Following technology advances of emerging nonvolatile memories (eNVM), applying eNVM to TCAM designs becomes attractive to achieve high density and low standby power. In this paper, we examined the applications of three promising eNVM technologies, i.e., magnetic tunneling junction (MTJ), memristor, and ferroelectric memory field effect transistor (FeFET), in the design of nonvolatile TCAM cells. All these technologies can achieve close-to-zero standby power though each of them has very different pros and cons.

Highly Sensitive Determination of Hydrazine Using Copper Hexacyanoferrate Nanoparticles Modified on Commercial Junction Field-Effect Transistor as Ion Sensitive Field-Effect Transistor

In this paper, for the first time, we introduce a simple and low cost hydrazine sensor based on a commercial junction field-effect transistor (JFET). The transistor was mechanically treated, isolated, and used as an ion sensitive FET (ISFET) for hydrazine detection, after the electrodeposition of the sensing membrane on its metal gate surface. Copper hexacyanoferrate nanoparticles as suitable sensing membrane were electrodeposited on the copper metal gate of transistor from a solution containing K4Fe(CN)6 by a cyclic voltammetry method. The prepared sensor showed a super-Nernstian response of 94.8 mV pHyd−1 over a linear concentration range of $1.17\times 10^{-5}$ – $2.15\times 10^{-2}$ M, a very low drift of 0.04 mV h−1, and the detection limit of $3.16~\mu \text{M}$ . Also, the various ISFET characteristics of the prepared sensor were studied and discussed.

JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.

A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets

In this paper, we propose and simulate a new structure of a line tunnel FET employing gate over source-channel overlap pockets (GO-SCOPs). The SCOPs create vertical tunneling path within the source and the channel extension that lead to a faster thinning of the lateral tunneling barrier between the source and channel regions. As a result, an inverted C-shaped tunnel junction is formed providing both lateral tunneling and vertical tunneling. A calibrated 2-D simulation study shows that an ON-current improvement by one order is achieved in comparison with the gate over source only (GoSo) tunnel field-effect transistors with pockets. Further, the OFF-state leakage and average subthreshold swing are reduced by 44% and 21%, respectively, with an improved parasitic capacitance. This has improved the cutoff frequency from 8.3 MHz in GoSo with pockets structure to 1.19 GHz in the proposed GO-SCOP structure. Furthermore, by employing Ge SCOPs, the ON current is boosted by 4 orders of magnitude, maintaining leakage at ~0.25 fA/μm, giving ION/IOFF > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , and a much improved average subthreshold swing of ~48 mV/dec at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 2 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V.

Effective measures for improving switching performance of SiC JFET bi‐directional switches

Silicon carbide (SiC)-based junction field-effect transistor (JFET) bi-directional switches (BDSs) have great potential in the construction of many power electronic circuits, including matrix converters, multi-level converters, solid-state breakers, and cycloconverters. However, the oscillations of BDSs during turn-on and turn-off transition have great impacts on the stability and reliability of power electronic systems. Two methods are proposed to improve the switching performance, namely using a snubber capacitor and using a ferrite ring. It is found that the use of a snubber capacitor mainly improves the turn-off transition, and the use of a ferrite ring not only damps the oscillation of current waveform during turn-on transition but also makes the waveforms cleaner and less noisy. Besides, both methods can cut down settling time significantly. The effects have been demonstrated by theoretical analysis and verified by experimental results.

Extraction method of interfacial injected charges for SiC power MOSFETs

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

ESD Robustness Enhancement Study of Ultra-High-Voltage JFET With Ballast Structure

Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure.