Junction Field Effect Transistor Research Articles

Characterization, Modeling and Design Parameters Identification of Silicon Carbide Junction Field Effect Transistor for Temperature Sensor Applications

Sensor technology is moving towards wide-band-gap semiconductors providing high temperature capable devices. Indeed, the higher thermal conductivity of silicon carbide, (three times more than silicon), permits better heat dissipation and allows better cooling and temperature management. Though many temperature sensors have already been published, little endeavours have been invested in the study of silicon carbide junction field effect devices (SiC-JFET) as a temperature sensor. SiC-JFETs devices are now mature enough and it is close to be commercialized. The use of its specific properties versus temperatures is the major focus of this paper. The SiC-JFETs output current-voltage characteristics are characterized at different temperatures. The saturation current and its on-resistance versus temperature are successfully extracted. It is demonstrated that these parameters are proportional to the absolute temperature. A physics-based model is also presented. Relationships between on-resistance and saturation current versus temperature are introduced. A comparative study between experimental data and simulation results is conducted. Important to note, the proposed model and the experimental results reflect a successful agreement as far as a temperature sensor is concerned.

High Temperature Performance of Normally-off SiC JFET's Compared to Competing Approaches

Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.

Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistormore » (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.« less

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances

Transient behavior in switching operation of junction field-effect transistors (JFETs) is affected by their intrinsic parasitic capacitances. This paper focuses on the switching operation of lateral-type and vertical-type SiC JFETs with considering the charge/discharge behavior of parasitic capacitances in the device. Their device structure decides the voltage dependency of the capacitance characteristics, so that the C-V characteristics governs their switching behavior.

Complementary logic with 60 nm poly gate JFET for 0.5 V operation

Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.

Crossbar heterojunction field effect transistors of CdSe:In nanowires and Si nanoribbons

Crossbar heterojunction arrays of n-CdSe:In nanowires (NWs) and p-Si nanoribbons (NRs) were built by ac electrical field-directed assembly. The junctions showed significant rectifying characteristics. With the p-Si NRs as gates, the junctions function as junction field effect transistors (JFETs) with high stability and reproducibility in performance. A small variation in gate voltage from −2 to −1 V was demonstrated to manipulate the current in n-CdSe:In NW channels by a factor near 103. The JFETs also showed a subthreshold swing value (67 mV/dec) approaching the theoretical limit (60 mV/dec), suggesting the great application potentials of the junctions in integrated nanoelectronics.

SiGe JFET과 Si JFET의 전기적 특성 비교

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and <TEX>$300\;{\mu}A$</TEX>, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

SiGe/Si/SiGe Channel을 이용한 JFET의 전기적 특성

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

Junction Field Effect Transistors for Nanoelectronics

The gate leakage currents of MOSFETs increase exponentially with downward scaling, while the gate currents of enhancement-mode JFETs for complementary logic decrease with scaling. In principle, a crossover point could exist below which the JFET may be the preferred device for some large-scale ICs. This paper first examines the crossover point with a simple scaling analysis that suggests it lies in the neighborhood of a 25 nm gate length, depending on the supply voltages and the gate insulator used for the MOSFET. Other JFET electrical properties compare favorably with those of MOSFETs and exhibit similar scaling behaviors. Numerical simulations of a simple 25 nm gate length JFET show electrical properties better than the conservative scaling analysis and comparable to reported 25 nm MOSFETs, with, for example, a gate current density of 12 A/cm2 at 0.7 V and a drain current on-to-off ratio of 3.5times103. A self-aligned polycrystalline silicon gate and some straightforward performance enhancements proposed for the 25 nm device may allow it essentially to stand in for the geometrically similar 25 nm MOSFET in some circumstances. Additional device engineering outlined in this paper should further allow the silicon JFET to scale down to 10 nm gate lengths, where source-drain tunneling becomes important. Ten-nanometer-scale JFETs share many of the fabrication challenges of corresponding MOSFETs, and many of the well-developed concepts for MOSFETs, such as double gates and strain engineering, should be easily adapted to JFETs. These devices also lend themselves to a subsequent transition to III-V semiconductors-for heterostructures, performance increases, and scaling below 10 nm-without the oxide interface problems MOSFETs would face. Overall, JFETs appear to be of interest for the next one to two silicon technology nodes, and perhaps beyond.

An ultralow noise preamplifier for low frequency noise measurements

Low frequency noise measurements are among the most sensitive tools for the investigation of the quality and of the reliability of semiconductor devices. The sensitivity that can be obtained depends on the background noise of the low noise preamplifier coupled to the device under test (DUT) that, at very low frequencies, is dominated by flicker noise. The low frequency noise produced by the DUT, on the other end, is very often the most interesting signal to be detected and analyzed. In this work we propose a very simple topology for the realization of a general purpose low noise preamplifier whose noise performances, at very low frequencies (below 10 Hz), are significantly better than those that can be obtained by the most popular commercial instrumentation. Indeed, a gain of 80 dB with a pass band extending from a few tens of mHz up to a few kHz with an equivalent input voltage noise as low as 14 nV/square root(Hz) (100 mHz), 1.4 nV/square root(Hz) (1 Hz), 1.0 nV/square root(Hz) (10 Hz), and 0.8 nV/square root(Hz) (1 kHz) are consistently obtained by using quite standard electronic components and with no need for trimming and/or calibration steps. Moreover, the junction field-effect transistor input stage of the amplifier is characterized by an equivalent input current noise below 4 fA/square root(Hz) in the entire bandwidth, resulting in negligible background noise degradation for DUT impedances in excess of 100 kohms.

SiC-VJFETs power switching devices: an improved model and parameter optimization technique

Silicon carbide junction field effect transistor (SiC-JFETs) is a mature power switch newly applied in several industrial applications. SiC-JFETs are often simulated by Spice model in order to predict their electrical behaviour. Although such a model provides sufficient accuracy for some applications, this paper shows that it presents serious shortcomings in terms of the neglect of the body diode model, among many others in circuit model topology. Simulation correction is then mandatory and a new model should be proposed. Moreover, this paper gives an enhanced model based on experimental dc and ac data. New devices are added to the conventional circuit model giving accurate static and dynamic behaviour, an effect not accounted in the Spice model. The improved model is implemented into VHDL-AMS language and steady-state dynamic and transient responses are simulated for many SiC-VJFETs samples. Very simple and reliable optimization algorithm based on the optimization of a cost function is proposed to extract the JFET model parameters. The obtained parameters are verified by comparing errors between simulations results and experimental data.

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

AbstractThis paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures.Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations.The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Extreme temperature 6H‐SiC JFET integrated circuit technology

AbstractExtreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh‐environment applications well above the 300 °C effective limit of silicon‐on‐insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H‐SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Enhanced Sensitivity of Small-Size (With 1-$\mu \hbox{m}$ Gate Length) Junction-Field-Effect-Transistor-Based Germanium Photodetector Using Two-Step Germanium Epitaxy by Ultrahigh Vacuum Chemical Vapor Deposition

In this letter, we demonstrate a scalable (with gate length of 1 mum) Ge photodetector based on a junction field-effect-transistor (JFET) structure with high sensitivity and improved response time. To overcome the low-detection-efficiency issue of typical JFET photodetectors, a high-quality Ge epilayer, as the gate of JFET, was achieved using a novel epigrowth technique. By laser surface illumination of 3 mW on the Ge gate, an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio up to 185 was achieved at a wavelength of 1550 nm for the first time. In addition, the device shows a temporal response time of 110 ps with a rise time of 10 ps, indicating that the scalable Ge JFET photodetector is a promising candidate to replace large-size photodiodes in future optoelectronic integrated circuits and as an image sensor integrated with a CMOS circuit for its comparable size in respect to modern MOSFETs.

A Low-Voltage Planar Power MOSFET With a Segmented JFET Region

A new low-voltage planar power MOSFET with a segmented junction field effect transistor (JFET) region is proposed and demonstrated in this paper. The segmented JFET region consists of alternating n- and p-regions formed by using ion implantation, and it is fully depleted before the drain-source breakdown voltage is reached to provide a high breakdown voltage. The new planar power MOSFET allows a smaller gate-drain overlap area, a shallower p-body, and a JFET region with a doping concentration higher than those of the conventional vertical double-diffused MOSFETs (VDMOSFETs). The new structure with a breakdown voltage of 34 V is fabricated by using a 0.5-mum technology and is compared with the conventional VDMOSFET. The gate-drain charge density and the figure-of-merit are improved by 51% and 48%, respectively. However, the specific on-resistance of the device is increased by 5% due to the smaller conducting area in the segmented JFET region. Simulation results show that the figure-of-merit of the new structure is very favorable compared to those of commercial devices at the same voltage rating.

6H-SiC JFETs for 450 $^{\circ}\hbox{C}$ Differential Sensing Applications

N-channel 6H-SiC depletion-mode junction field-effect transistors (JFETs) have been fabricated, and characterized for use in high-temperature differential sensing. Electrical characteristics of the JFETs have been measured and are in good agreement with predictions of an abrupt-junction long-channel JFET model. The electrical characteristics were measured across a 2-in wafer for temperatures from 25degC to 450degC, and the extracted pinchoff voltage has a mean of 11.3 V and a standard deviation of about 1.0 V at room temperature, whereas pinchoff current has a mean of 0.41 mA with standard deviation of about 0.1 mA. The change in pinchoff voltage is minimal across the measured temperature range, whereas pinchoff current at 450degC is about half its value at room temperature, consistent with the expected change in the nmu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> product. The characterization of differential pairs and hybrid amplifiers constructed using these differential pairs is also reported. A three-stage amplifier with passive loads has a differential voltage gain of 50 dB, and a unity-gain frequency of 200 kHz at 450degC, limited by test parasitics. A two-stage amplifier with active loads has reduced sensitivity to off-chip parasitics and exhibits a differential voltage gain of 69 dB with a unity-gain frequency of 1.3 MHz at 450degC.

Silicon Integrated Waveguide Modulator Based on a Three-Terminal Device Structure

We report a comprehensive study on the silicon optical waveguide modulators fabricated with and without the isolation trenches based on a modified structure of junction field-effect transistor (JFET). The particular emphases are dedicated to elucidating the influences of various device dimensions on their corresponding modulation efficiencies and frequency responses. Specifically, the enhancement in the modulation depth of the devices was clearly observed as their rib waveguide widths or modulation lengths became respectively wider or longer. In fact, a nearly 100% modulation index could be achieved with a bias voltage as low as 4 V. Furthermore, the modulation efficiency of the devices was evidently improved with a substantial degree by adopting a three-terminal JFET structure for signal modulation; the lowest rise and fall times obtained were 250 and 400 µs, respectively. Finally, adding trenches to each side of the rib seemed to impede the carriers flow, thereby slowing down the carrier injection or accumulation speed during the actual device operation.

Design Considerations for CdTe Nanotetrapods as Electronic Devices

We investigate the feasibility of using CdTe nanotetrapods as circuit elements using models and simulation at multiple scales. Technology computer-aided design tools are used to simulate the electrical behavior for both metal-semiconductor field-effect transistors and junction field-effect transistors. Our results show that by varying the doping concentrations and material composition, CdTe nanotetrapods have the potential to be useful circuit elements. Monte Carlo simulations provide insight into how control over interparticle and particle-substrate interactions can lead to the directed assembly of ordered arrays of electrically gated nanotetrapods.

Prolonged 500 °C Operation of 6H-SiC JFET Integrated Circuitry

This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.

Effect of Bipolar Gate-to-Drain Current on the Electrical Properties of Vertical Junction Field Effect Transistors

Electron-hole recombination-induced stacking faults have been shown to degrade the I-V characteristics of SiC power p-n diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effect of bipolar gate-to-drain current on vertical-channel JFETs. The devices have n- drift epitaxial layers of 12-μm and 100-μm thicknesses, and were stressed at a fixed gate-to-drain current density of 100 A/cm2 for 500 hrs and 5 hrs, respectively. Significant gate-to-drain and on-state conduction current degradations were observed after stressing the 100-μm drift VJFET. Annealing at 350°C reverses the stress induced degradations. After 500 hours of stressing, the gate-to-source, gate-to-drain, and blocking voltage characteristics of the 12-μm VJFET remain unaffected. However, the on-state drain current was 79% of its pre-stress value. Annealing at 350°C has no impact on the post-stress on-state drain current of the 12-μm VJFET. This leads us to attribute the degradation to a “burn-in” effect.