Junction Field Effect Transistor Structure Research Articles

Device and Circuit Design for Improving the Freewheeling Characteristics of High Voltage Monolithic Integrated Circuit

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch-off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off-state. Adopting the new freewheeling circuit, the reverse recovery charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RR</sub> ) and the peak reverse recovery current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RRM</sub> ) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process.

Novel partially depleted SOI MOSFET for suppression floating-body effect: An embedded JFET structure

Silicon-on-insulator (SOI) devices have an inherent floating body effect which may cause substantial influences in the performance of SOI devices and circuits. In this paper we propose a novel device structure to suppress the floating body effect by using an embedded junction field effect transistor (JFET). The key idea in this work is to provide a path for accumulated holes to flow out of the body to improving of electrical performance. We have introduced a p+-Si1−xGex buried region under the n+-Si1−xGex source and called the proposed structure as embedded JFET SOI MOSFET (EJFET–SOI). Using two-dimensional two-carrier simulation, the output and subthreshold characteristics of EJFET–SOI are compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the EJFET–SOI structure as expected without consuming a significant amount of area.

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

AbstractThis paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures.Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations.The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Silicon Integrated Waveguide Modulator Based on a Three-Terminal Device Structure

We report a comprehensive study on the silicon optical waveguide modulators fabricated with and without the isolation trenches based on a modified structure of junction field-effect transistor (JFET). The particular emphases are dedicated to elucidating the influences of various device dimensions on their corresponding modulation efficiencies and frequency responses. Specifically, the enhancement in the modulation depth of the devices was clearly observed as their rib waveguide widths or modulation lengths became respectively wider or longer. In fact, a nearly 100% modulation index could be achieved with a bias voltage as low as 4 V. Furthermore, the modulation efficiency of the devices was evidently improved with a substantial degree by adopting a three-terminal JFET structure for signal modulation; the lowest rise and fall times obtained were 250 and 400 µs, respectively. Finally, adding trenches to each side of the rib seemed to impede the carriers flow, thereby slowing down the carrier injection or accumulation speed during the actual device operation.

Junction field-effect-transistor-based germanium photodetector on silicon-on-insulator

We propose and demonstrate a novel Ge photodetector on silicon-on-insulator based on a junction field effect transistor structure, where the field-effect transistor gate is replaced by a Ge island with no contact on it. Light incident on the Ge switches on the device by altering the conductance of the Si channel through secondary photoconductivity. The device's sensitivity is also enhanced by a vast reduction in parasitic capacitance. In cw measurements, proof-of-concept detectors exhibit up to a 33% change in Si channel conductance by absorbing only 200 nW of power at 1.55 microm. In addition, pulsed response tests have shown that rise times as low as 40 ps can be achieved.

Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor

In this letter, a novel type of high-voltage n-channel junction field-effect transistor (JFET) was designed using a conventional n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) without changing any step in the process. High-voltage JFET can be a start-up device in power factor correction, dc-ac converters, and ac-dc converters for providing a self-powered circuit and minimizing standby power losses without gate control because of its negative threshold voltage. Experimental results show that an n-LDMOS with this JFET structure can achieve a reverse blocking voltage of more than 700 V with very low leakage current. The pinch-off voltage can be designed by changing n-well width to meet the circuit requirement.

Design Criteria of High-Voltage Lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.

Application of a Junction Field Effect Transistor Structure to a Low Loss Diode

A novel low loss diode with junction grids has been proposed. Numerical simulations reveal that, for this diode, designing a submicron grid width improves the tradeoff characteristics between the forward voltage drop and the leakage current, leading to characteristics superior to those of the Schottky barrier diode. The introduction of a lateral silicon-on-insulator (SOI) structure into the proposed diode is attractive for achieving such a small grid width. The simulation also demonstrates design methods for channel doping and thickness of the buried oxide layer in the SOI diode.

Hydrogen-free amorphous carbon preparation and properties

Amorphous carbon containing very little hydrogen and having a highly tetrahedral character is deposited by filtered cathodic arc. This amorphous carbon shows photoconductivity under white light illumination. It is slightly p-type in pure form but becomes n-type when doped with nitrogen. Electron diffraction shows that nitrogen levels of less than 1% do not distort the tetrahedral network, but at higher concentrations nitrogen destabilises the tetrahedral structure. Plasmon spectroscopy shows the presence of a 1 nm “defective” surface layer even in the pure material which has implications for device applications. A junction field effect transistor structure is proposed as a possible device.

Modelling of the depleted p-JFET radiation detector

The feasibility of a depleted junction field effect transistor (JFET) detector structure which is a combined radiation detector and low-noise charge readout transistor is studied computationally. The operating principle of the depleted p-JET detector incorporating a p-channel JFET structure processed on the surface of a high-resistivity n-type silicon chip is described. Results from two-dimensional potential and charge carrier concentration simulation of the structure indicate that the charge signal can be successfully read out by the FET provided that an appropriate doping profile shape is implemented in the device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Depletion and enhancement mode In0.53Ga0.47As/InP junction field-effect transistor with a p+-InGaAs confinement layer

A self-aligned all-In0.53Ga0.47 As junction field-effect transistor structure grown by molecular beam epitaxy is described, using p+-InGaAs as the confinement layer for the n channel. Devices have been made to operate in either the depletion mode or the enhancement mode. Transconductances of 90 mS/mm have been observed, with low capacitance (0.7 pF/mm) and low gate leakage.

Subsurface junction field effect transistor

A novel bipolar compatible junction field effect transistor structure is described in this paper. The device is fabricated using a single boron implant at energies high enough to result in a p-type channel fully embedded in an n-epitaxial background material. The channel is buffered from the Si-SiO 2 interface by a thin n-type region which improves device reproducibility. The structure has been used to make subvolt pinchoff devices especially suitable for micropower low voltage operation.