Junction Edge Research Articles

Improving medial surfaces for reverse engineering

ABSTRACTCommon medial axis transform methods create two artifacts: shrinkage of the end of surfaces and small dent at junctions. They are due to the definition of medial axis transforms and they are bottlenecks in industrial applications. This paper presents two methods to improve the medial surfaces computed from CT images of thin-plate mechanical objects. We first introduce a method for extending the ends of medial surfaces by finding the intersection points of medial voxels on the isosurface. We also propose a method to remove dent structures at junction edges by minimizing error functions. These improvements, integrated into a conventional medial surface extraction method using sub-sampling, resolve several drawbacks in reverse engineering applications.

High-k Dielectric Passivation for GaN Diode with a Field Plate Termination

Vertical structured Gallium nitride (GaN) p-n junction diodes with improved breakdown properties have been demonstrated using high-k dielectric passivation underneath the field plate. Simulation results at a reverse voltage of 1 kV showed that the maximum electric field near the mesa-etched p-n junction edges covered with film of dielectric constant k = 10 was reduced to 2.0 MV/cm from 3.0 MV/cm (SiO2 (k = 3.9)). The diodes were fabricated using the high-k mixed oxide of SiO2 and CeO2 with k = 12.3. I–V characteristics of the diode with a field plate showed a breakdown voltage above 2 kV with an increased avalanche resistance. This means that the electric field reduces at the periphery of the mesa-etched p-n junction and is uniformly formed across the whole p-n junction. It is clear that high-k dielectric film passivation and filed plate termination are essential techniques for GaN power devices.

A computational method for modeling arbitrary junctions employing different surface integral equation formulations for three-dimensional scattering and radiation problems

This paper presents a new method, based on the well-known method of moments (MoM), for the numerical electromagnetic analysis of scattering and radiation from metallic or dielectric structures, or both structure types in the same simulation, that are in contact with other metallic or dielectric structures. The proposed method for solving the MoM junction problem consists of two separate algorithms, one of which comprises a generalization for bodies in contact of the surface integral equation (SIE) formulations. Unlike some other published SIE generalizations in the field of computational electromagnetics, this generalization does not require duplicating unknowns on the dielectric separation surfaces, except duplications for a very small fraction of unknowns corresponding to junction edges, which introduces a negligible computational cost. Additionally, this generalization is applicable to any ordinary single-scatterer SIE formulations employed as baseline. The other algorithm deals with enforcing boundary conditions and Kirchhoff’s Law, relating the surface current flow across a junction edge. Two important features inherent to this latter algorithm consist of a mathematically compact description in matrix form, and importantly, from a software engineering point of view, an easy implementation in existing MoM codes which makes the debugging process more comprehensible. A practical example involving a real grounded monopole antenna for airplane-satellite communication is analyzed for validation purposes by comparing with precise measurements covering different electrical sizes.

Seismic images of the mantle transition zone beneath Northeast China and the Sino-Korean craton from P-wave receiver functions

Seismic data from northeast (NE) China and the Sino-Korean craton were combined to image the upper mantle discontinuities at 410 and 660km. Fine-scale topographic variations on these two discontinuities provide important clues for both delineating geometry of the subducting Pacific slab particularly at arc–arc junction and interpreting regional Cenozoic intraplate volcanism. We used over 90,000 receiver functions from 1916 teleseismic earthquakes recorded by 584 broadband seismic stations, primary those of temporary seismic arrays. We found the average depths of the two discontinuities to be 410km and 672km, respectively, beneath the study area. Results show that the 660-km discontinuity is strongly depressed by about 20–30km in a narrow region beneath and around the Changbaishan volcano, consistent with the results of previous receiver function studies. In contrast, much of the Sino-Korean craton exhibits typical transition zone thickness (~260km) and thus offers no evidence of a stagnated Pacific slab. Our results also reveal an elevated 660-km discontinuity and a thinner transition zone both to the west of the observed depression region and beneath the Kuril–Japan arc junction. This feature is most likely due to a tearing of the descending Pacific plate at both its leading and junction edges. An additional elevated 660-km discontinuity together with a thinner transition zone appears in the vicinity of the Dariganga lava field, supporting interpretations of a deep-rooted mantle plume. Our observations of an elevated 410-km discontinuity and a thicker transition zone correlate spatially with the diffuse distribution of volcanism around Hannuoba, Aershan and Wudalianchi. This correlation may suggest lithospheric removal as a mechanism for these magmatic activities.

BinPacker: Packing-Based De Novo Transcriptome Assembly from RNA-seq Data

High-throughput RNA-seq technology has provided an unprecedented opportunity to reveal the very complex structures of transcriptomes. However, it is an important and highly challenging task to assemble vast amounts of short RNA-seq reads into transcriptomes with alternative splicing isoforms. In this study, we present a novel de novo assembler, BinPacker, by modeling the transcriptome assembly problem as tracking a set of trajectories of items with their sizes representing coverage of their corresponding isoforms by solving a series of bin-packing problems. This approach, which subtly integrates coverage information into the procedure, has two exclusive features: 1) only splicing junctions are involved in the assembling procedure; 2) massive pell-mell reads are assembled seemingly by moving a comb along junction edges on a splicing graph. Being tested on both real and simulated RNA-seq datasets, it outperforms almost all the existing de novo assemblers on all the tested datasets, and even outperforms those ab initio assemblers on the real dog dataset. In addition, it runs substantially faster and requires less memory space than most of the assemblers. BinPacker is published under GNU GENERAL PUBLIC LICENSE and the source is available from: http://sourceforge.net/projects/transcriptomeassembly/files/BinPacker_1.0.tar.gz/download. Quick installation version is available from: http://sourceforge.net/projects/transcriptomeassembly/files/BinPacker_binary.tar.gz/download.

高誘電率絶縁膜を用いたフィールドプレート電極を有する縦型GaNダイオード

GaN high voltage diodes with high-k dielectrics passivation underneath the filed plate are demonstrated. Simulation results at reverse voltage of 1000V showed that the maximum electric field near the mesa-etched pn junction edges covered with film of dielectric constant k value of 10 was reduced to 2.3MV/cm from 3.2MV/cm (SiO2(k=3.9)). Mesa structures of pn junction diodes were fabricated by ICP dry etching, and mixed oxide of SiO2 & CeO2 dielectric film with k value of about 12.3 was deposited by CVD. I-V characteristics of the diode with a field plate showed the breakdown voltage above 2000 V with an increased avalanche current. This means that the electric field reduces at the periphery of the mesa etched pn junction and was uniformly formed across the whole pn junction. It is clear that high-k dielectric film passivation and filed plate termination are essential techniques for GaN power devices.

A Novel Drain Design for ESD Improvement of UHV-LDMOS

This paper investigates the electrostatic discharge (ESD) failure mechanism in the human body model of circular ultrahigh voltage lateral diffused MOS-type devices. Failure occurs due to the current crowding effect at the N+ junction edge of the drain adjacent to the field oxide. Instead of a large single N+ diffusion, a novel drain design with small multidiffusions is proposed to eliminate the current crowding and to enhance its ESD performance.

Analysis of Source Doping Effect in Tunnel FETs With Staggered Bandgap

The effect of source doping on tunnel FET (TFET) currents is investigated analytically for the case of an exponential barrier. Source depletion is coupled to the channel potential profile through the continuity of field at the junction edge. Closed form WKB (Wentzel-Kramers-Brillouin) integral are carried out by considering mixed electron and hole tunneling in heterojunction TFETs with a staggered bandgap. It is shown that there is an optimum source doping that maximizes the TFET current. A certain degree of source depletion actually helps because it lets low-barrier hole tunneling in the source to make up part of the tunneling path.

The Blue LED Nobel Prize: Historical context, current scientific understanding, human benefit

The Blue LED Nobel Prize: Historical context, current scientific understanding, human benefit

Behaviour of stiffened cold-formed steel built-up sections with complex edge stiffeners under bending

This paper is concerned with the effect of stiffened element at the flange/web junction and complex edge stiffener in behaviour and strength of built-up cold-formed steel flexural members. An extensive experimental investigation and a finite element analysis of stiffened built-up cold-formed beam sections with complex stiffeners under two point loading is presented. A nonlinear finite element model is developed and verified against test results. All the results are compared with the design strength calculated using the North American Iron and Steel Institute Specification for cold-formed steel structures (AISI: S100, 2007). Following the validation, an extensive finite element parametric study is conducted to study the influences of a range of parameters, and the results are compared with the nominal design strength by AISI: S100 (2007) and suitable recommendation are made.

Two-dimensional magnetic field dependence of zero and finite voltage steps in current–voltage characteristics of superconducting quantum interference devices

Modulation characteristics of Josephson current through superconducting quantum interference devices (SQUIDs) by two dimensional scanning of external magnetic field have been studied. Vertical type SQUIDs composed of two niobium/aluminum-oxide/niobium (Nb/Al-oxide/Nb) tunnel junctions are fabricated using magnetron sputtering system. In order to measure the magnetic dependence of the critical current Ic through SQUIDs, Hx and Hy magnetic field components parallel to junction edges are scanned in two dimensions (2-D) by using two pairs of Helmholtz coils driven in GPIB (General Purpose Interface Bus) system. The 2-D magnetic field (Hx, Hy) dependences of the Josephson current Ic and the resonant current steps Istep at finite voltage in the current–voltage curves of SQUIDs have been obtained. Modulation characteristics of SQUIDs with different junction separation are measured. The resonant current steps Istep are also studied using superconducting planar circuit model.

Practical aspects of the cellular force inference toolkit (CellFIT).

If we are to fully understand the reasons that cells and tissues move and acquire their distinctive geometries during processes such as embryogenesis and wound healing, we will need detailed maps of the forces involved. One of the best current prospects for obtaining this information is noninvasive force-from-images techniques such as CellFIT, the Cellular Force Inference Toolkit, whose various steps are discussed here. Like other current quasistatic approaches, this one assumes that cell shapes are produced by interactions between interfacial tensions and intracellular pressures. CellFIT, however, allows cells to have curvilinear boundaries, which can significantly improve inference accuracy and reduce noise sensitivity. The quality of a CellFIT analysis depends on how accurately the junction angles and edge curvatures are measured, and a software tool we describe facilitates determination and evaluation of this information. Special attention is required when edges are crenulated or significantly different in shape from a circular arc. Because the tension and pressure equations are overdetermined, a select number of edges can be removed from the analysis, and these might include edges that are poorly defined in the source image, too short to provide accurate angles or curvatures, or noncircular. The approach works well for aggregates with as many as 1000 cells, and introduced errors have significant effects on only a few adjacent cells. An understanding of these considerations will help CellFIT users to get the most out of this promising new technique.

Study on HK-VDMOS with Deep Trench Termination

A structure of junction edge termination for the High-K Vertical Diffused Metal Oxide Silicon (HK-VDMOS) is proposed and studied. It consists of two deep trenches filled with SiO2 and HK dielectric, respectively. The former is mainly used to sustain the surface high voltage, which significantly contributes to reduce the termination width. The latter transmits the strong electric field in the SiO2 into the source electrode before it reaches the inside HK-VDMOS cells, which ensures the optimized electric field distribution of the inside HK-VDMOS cells is not affected. Therefore, for the total device with termination, high breakdown voltage and ultralow specific on-resistance as well as very small termination width can be simultaneously obtained. Numerical simulation shows that, for an N-type HK-VDMOS (the permittivity is set as K=300) with the proposed termination, the Ron,sp of 26.4mΩcm2 is achieved at a breakdown voltage of 743V, where the termination width is only 14μm.

Switching times in long-overlap Josephson junctions subject to thermal fluctuations and non-Gaussian noise sources

We investigate the superconducting lifetime of long current-biased Josephson junctions, in the presence of Gaussian and non-Gaussian noise sources. In particular, we analyze the dynamics of a Josephson junction as a function of the noise signal intensity, for different values of the parameters of the system and external driving currents. We find that the mean lifetime of the superconductive state is characterized by nonmonotonic behavior as a function of noise intensity, driving frequency and junction length. We observe that these nonmonotonic behaviours are connected with the dynamics of the junction phase string during the switching towards the resistive state. An important role is played by the formation and propagation of solitons, with two different dynamical regimes characterizing the dynamics of the phase string. Our analysis allows to evidence the effects of different bias current densities, that is a simple spatially homogeneous distribution and a more realistic inhomogeneous distribution with high current values at the junction edges. Stochastic resonant activation, noise enhanced stability and temporary trapping phenomena are observed in the system investigated.

Investigation on the Corner Effect of <I>L</I>-Shaped Tunneling Field-Effect Transistors and Their Fabrication Method

In this work, electrical characteristics of L-shaped tunneling field-effect transistors (TFETs) have been studied and optimized by a commercial device simulator: Synopsys Sentaurus. Unlike our previous study performed by using Silvaco Atlas, there exists a kink phenomenon in a transfer curve which degrades the subthreshold swing (SS) and on-current (lon) of TFETs. According to simulation results, the kink results from abrupt source doping. Rounding the source junction edge with gradual doping profile is helpful to alleviate it. Based on those results, a novel fabrication flow has been proposed to suppress the kink effect induced by source corners. It is predicted that the performance of L-shaped TFETs is improved in terms of SS and Ion under the optimized process condition. Furthremore, the effect of high-k gate dielectric and narrow band gap material on device performance has been examined. Using 2-nm-thick HfO2 for gate dielectric and Si0.7Ge0.3 for intrinsic tunneling region, gate controllability to the channel and tunneling probability have been enhanced. As a result, its threshold voltage (Vth), SS and Ion have been improved by 0.13 V, 16 mV/dec, and 3.62 microA/microm, respectively.

New Planar Junction Edge Termination Technique Using OPTVLD With a Buried Layer

A new planar junction edge termination technique, using the optimum variation lateral doping with a buried layer, is proposed and studied. A voltage equal to 100% of the breakdown voltage of a single-sided abrupt parallel-plane junction with the same substrate can be achieved within a smallest area on the surface. The proposed technique can be realized by a process compatible with conventional CMOS or BiCMOS technologies and verified by the results of numerical simulations.

A Four-Bit-Per-Cell Program Method with Substrate-Bias Assisted Hot Electron Injection for Charge Trap Flash Memory Devices

We propose a four-bit-per-cell program method using a two-step sequence with substrate-bias assisted hot electron (SAHE) injection into the charge trap flash memory devices in order to overcome the limitations of conventional four-bit program methods, which use channel hot electron (CHE) injection. With this proposed method, a localized charge injection near the junction edge with an acceptable read margin was clearly observed, along with a threshold voltage difference of 1 V between the forward and the reverse read. In addition, a multi-level storage was easily obtained using a drain voltage step of 1 V at each level of the three programmed states, along with a fast program time of 1 micros. Finally, by using charge pumping methods, we directly observed the detailed information on the spatial distribution of the local threshold voltage in each level of the four states, for each physical bit, as a function of the program voltage.

Towards Very High Voltage SiC Power Devices

The development of high voltage devices is a great challenge. At least, railway and high voltage distribution network are example of applications requiring high voltage devices. SiC power devices and technology seems to be mature enough to give a short term solution. Indeed, silicon carbide devices appear to be the semiconductor of choice for high voltage (> 6.5 kV) applications compared to Gallium Nitride and Diamond. For high voltage devices, periphery protection is mandatory in order to reduce the well-known electric field crowding taking place at the junction edge. Some details are given about the different periphery technics (JTE, guard rings, MESA) applied to SiC devices, before combining some of them to reach higher and higher breakdown voltages. Some works remaining to be done are given as a conclusion of this paper.

Anomalous modulation characteristics of DC Josephson current through niobium tunnel junction by applying external magnetic field 4000A/m in perpendicular direction

Graphical abstractDisplay Omitted Through Nb superconducting junction with Al-oxide current flow without voltage drop.Josephson current Ic dependence on Hx, Hy and Hz magnetic field was obtained.Ic dependence on Hx, Hy before applying Hz was Fraunhofer pattern.Ic dependence on Hx, Hy after applying Hz was not Fraunhofer pattern.Numerical simulation explained the measured dependence. Anomalous modulation characteristics of Josephson current Ic through niobium tunnel junctions at liquid helium temperature were first measured after applying the external magnetic field in perpendicular direction. Josephson current Ic was modulated by applying the external magnetic fields (Hx, Hy) parallel and Hz vertical to the junction plane. Modulation characteristics of the Ic value upon Hz had hysteresis. Before applying the vertical field, modulation characteristics Ic-(Hx, Hy) were the product of the two Fraunhofer diffraction patterns in Hx and Hy directions which were parallel to the junction edges of the square shape junction, respectively. Under the perpendicular magnetic field as much as 4000A/m, the maximum Ic value did not appear at (Hx, Hy)=(0, 0) point. After removing this vertical field, the Ic-(Hx, Hy) modulation pattern changed from the product of the two Fraunhofer diffraction patterns to the deformed Ic-(Hx, Hy) characteristics, whose anomalous shape was explained by assuming the extremely low current density at four edges of the square shape except the four corner regions. Some magnetic flux would be trapped perpendicularly inside the junction electrodes within the junction area. After the junction was heated to the room temperature and was again cooled to the liquid He temperature, these modulation characteristics again became the normal modulation pattern, in which the trapped flux would be released by this thermal cycle.

Analysis of the thermal stress and warpage induced by soldering in monocrystalline silicon cells

Silicon-based solar applications have tended toward the use of large, thin cells. However, an increased loss of materials occurs due to a high rate of destruction during the soldering and packaging processes. This study adopted various material parameters as variables and used the finite element method (FEM) to analyze the thermal stress and warpage induced by the temperature changes of the soldering process. The results demonstrate that hot-air (for soldering) temperature changes do not affect the cell warpage significantly. The significant factors affecting cell warpage include cell thickness, soldering rod thickness, and soldering rod width. The residual stress on the cell is localized at the junction edge between the soldering rods and cell and is broadly aligned with the typical locations of cell damage after the soldering process. The main parameters affecting the residual thermal stress of the cell are the temperature of the hot-air, cell thickness, soldering rod thickness, and soldering rod width.