Josephson Junction Logic Research Articles

Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Josephson junction logic cells and superconductor microstrip lines are able to process and transfer digital data with rates up to several hundred GHz as has been demonstrated in single-chip experiments. However, the existing chip-level bumping technique in InSn solder and resulting inter-chip connections do not allow expanding these rates to multi-chip circuits. We developed a wafer-level bumping technology using lithographically-defined bumps deposited either by e-beam evaporation or electroplating, and proposed and implemented a novel design of high-frequency chip interconnects. Chip-to-chip single-flux-quantum pulse transmission rates reaching 110 GHz have been achieved. The observed rates were limited not by the interconnects but by the speed of on-chip test circuitry fabricated in the framework of 4.5 <formula formulatype="inline"> <tex Notation="TeX">${\rm kA/cm}^{2}$</tex></formula> HYPRES process for superconductor integrated circuits. Experimental results on adhesive-bonded and reflow-bonded multi-chip modules (MCMs) with Au and InSn bumps are presented, and effective parameters of the new interconnect design and MCM technology are discussed. </para>

A new approach for analysis of on-chip interconnections in integrated Josephson junction logic schemes

Currently, clock speeds of up to 100 GHz of the superconducting digital circuitson the base of the propagation of single flux quanta are under consideration.In order to make full use of the high operation speed,limitations due to the interconnections are investigated using a new analysismethod. The modelling is described and a comparison to a conventional approach is made.The results provide conditions of practical use for the interconnect design on chip-level.

Analysis of electromagnetic coupling effects in integrated Josephson junction logic devices by the FDTD technique

A very important step of the design of circuits and devices in the Josephson junction technology is the complete and correct calculation of their electrical characteristics. Due to the very high clock speed of up to 100 GHz, dynamic effects like the electromagnetic coupling start to play a significant role over the operation of the system. The presented work reports on the implementation of the FDTD technique for the description of the electromagnetic coupling effects in the Josephson devices. Some typical microstrip layouts are considered strictly taking in account the technological specifications. The obtained results are analyzed in respect to the constraints, which the coupling effects impose on the lateral dimensions of the microstrip lines.

Future heat transfer concerns in Josephson junction computers

Using the superconducting properties of Josephson junctions enable extremely high switching speeds unmatched in semiconducting electronics. Much research has been conducted in recent decades in order to produce high performance electronics based on Josephson junction logic. In addition to the high speeds attainable by this technology, also of significance is the very low heat dissipated by Josephson circuits. Josephson devices have made great strides in the last ten years with microprocessors reaching levels of integration as high as 10/sup 5/ junctions/cm/sup 2/. Dissipation in these devices is easily managed, but integrations reaching 10/sup 7/ must be considered if Josephson electronics are to compete with the complexity and functionality of semiconducting electronics. Coupling this level of integration with dissipations of 0.34 and 2.98 /spl mu/W/junction in low and high temperature cases respectively, produces large heat fluxes difficult to remove at cryogenic temperatures. While other technical difficulties currently overshadow heat transfer concerns, the future of Josephson electronics research will likely need to address them.

FD-TLM electromagnetic field simulation of high-speed Josephson junction digital logic gates

The finite-difference transmission line matrix (FD-TLM) method is extended to modeling low-T/sub c/ Josephson junction (JJ) digital logic integrated circuits (IC's), providing comprehensive simultaneous time-domain, three-dimensional (3-D) full-wave electromagnetic field and JJ device analysis. Techniques for FD-TLM modeling of a Josephson Atto-Webber switch (JAWS), a two-junction superconducting quantum interference device (SQUID), and modified variable threshold logic (MVTL) logic gates are discussed and simulation results are presented. Interconnection lengths are intentionally short so that the full-wave FD-TLM simulation results can be validated with results of conventional quasistatic-based circuit simulations. Good agreement between the simulation techniques validates the FD-TLM JJ logic circuit modeling approach. In the FD-TLM method the electromagnetic behavior of the circuit is modeled from the material properties and dimensions of the circuit, avoiding separate extractions of parasitic capacitance and inductance as needed in conventional circuit simulations.

Superconductive crossbar system for communication applications

This paper reviews current efforts toward the integration of a high-speed crossbar switch for digital communication applications. This system is an intelligent switching matrix for 128 inputs and 128 outputs, each capable of 2 Gbs (10 9 bits per second). An array of Josephson junction integrated circuits are interconnected with the use of a superconductive multichip module maintained at 4.2 K. This module is connected to room-temperature electronics by means of flexible cables, each containing impedance-matched microstrip transmission lines. Room-temperature interface electronics will permit interconversion between standard level input/output signals and Josephson junction logic levels.

Attojoule MOSFET logic devices using low voltage swings and low temperature

Previous estimates of the performance limits of MOSFET logic devices, including the possibility of low temperature operation, have used the conventional static electrical behavior as a starting point. Typically, such studies conclude that the minimum voltage swing is ∼ 200 mV, leading to practical limits on power dissipation and switching speed that prohibit the combination of very low-power dissipation and very high speed achieved in Josephson junction logic. At such low voltages, the device behavior becomes very sensitive to fabrication, making high yields difficult. Here we consider the conditions which must be met to achieve high speed and low power VLSI logic devices through voltage swings ∼ 25 mV. Dynamic logic through bulk conduction devices operating at T ≲ 30K represents the major requirements. At such low temperatures, nonequilibrium processes provide a new basis for device action, and a novel relaxation mode MOSFET operating under carrier freezeout conditions is suggested as a possible low-voltage swing logic switch with power-delay products in the attojoule range.

Analysis of flux input and output Josephson pair device

A new Josephson junction logic device working on the principle of parametron and operated entirely on dc flux for input, output and excitation is discussed in this article. Computer simulation of the device operation with clock signal of 100psec shows that the device is behaving very well as a logic element with very low power dissipation. The device's parameters and noise problems such as thermal noise and quantum tunnelling noise are also discussed. Promising results are obtained from the analysis.

Lead alloy Josephson junction direct injection logic gates

A new group of high gain, wide margin direct injection Josephson junction logic gates including a three Josephson junction OR (3J/OR) and a four Josephson junction AND (4J/AND) was previously described. In the present work, these gates have been fabricated in an improved lead alloy technology using 5μm design rules. The measured threshold curves of the 3J/OR and the 4J/AND are in good agreement with the theoretical predictions despite the fact that current density and sheet resistance of the samples differed from the design values.

Thermally induced vortex-to-vortex transitions in a superconducting quantum interference device

Thermally induced vortex-to-vortex transitions between the zero-quantum vortex state and one- flux-quantum vortex state of a symmetric two-junction dc superconducting quantum interference device (SQUID) have been observed. The characterization of transitions of this type is an essential part of the modeling of Josephson junction logic and memory devices. The transition rates, measured as a function of bias current, applied flux, and temperature, are in excellent agreement with rates predicted by a thermal activation model for two-junction SQUID’s.

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).

A comparison of semiconductor devices for high-speed logic

The bipolar transistor and FET are compared, considering both today's most advanced implementations and "ultimate" scaled-down devices. The differences between the devices are quantified in terms of transconductance and intrinsic speed. Old limits are re-examined and ways of extending the devices toward their ultimate in performance are proposed. While the major emphasis is on silicon, a comparison is made with the GaAs MESFET. Other semiconductor devices are discussed in the context of "bipolar-like" and "FET-like" devices, and the HEMT is considered a very promising candidate for high-speed logic. While Josephson junction logic is not discussed at length, it is a continual point of reference. In addition to comparing devices, the on-chip wiring environment is discussed, especially concerning its impact on power-delay products.

Josephson logic circuit with a sinusoidal current supply

We propose here a method of powering latching-type Josephson junction logic circuits by a high-frequency sinusoidal source, allowing parallel connection and automatic resetting during each zero crossing of the supply. Analytical guidelines useful in the design of such circuits are developed.

Quantum interference Josephson logic devices

Experiments with latching and nonlatching quantum interference logic devices are described. The device is a three-junction interferometer, switching with control currents of &amp;lt;0.5 mA. Simple logic functions have been performed with dc-powered nonlatching devices having a power dissipation of &amp;lt;40 nW in continuous operation.