Phase-locked Loop Jitter Research Articles

A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication-Link Noise

A phase-locked-based frequency synthesizer – ubiquitously used to generate local oscillation in a communication transceiver – exhibits phase noise and jitter which considerably degrades bit-error rate (BER) and error vector magnitude (EVM) of a digital communication link. This paper presents an analytical study of EVM and BER degradation for a variety of widely used digital modulation schemes. Phase noise and jitter of a generic integer-N phase-locked loop (PLL) as a local oscillator feeding an RF mixer are derived, while accounting for the reference spurs and cyclo-stationarity of the mixer operation as well as the additive noise of the communication link. This jitter model is then utilized to directly study its impact on digital modulation constellations. Specifically, the EVM and BER degradation due to the PLL jitter in communication systems incorporating M-ary phase-shift keying (M-PSK) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${4^{M}}$ </tex-math></inline-formula> quadrature amplitude modulation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${4^{M}}$ </tex-math></inline-formula> QAM) are analyzed. Comparison between analytical models and system-level simulations verifies an excellent accuracy of these models.

A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only $53~\mu \text{W}$ , which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fsrms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a figure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

A low jitter phase-locked loop based on self-biased techniques

A low jitter phase-locked loop based on self-biased techniques

Correlation of scintillation occurrence with interplanetary magnetic field reversals and impact on Global Navigation Satellite System receiver tracking performance

Ionospheric scintillation is characterized by rapid fluctuations in the amplitude and phase of transionospheric radio signals as they pass through small scale ionospheric plasma density irregularities. Over the auroral regions, the occurrence of scintillation is associated with large‐scale plasma structures and is mainly enhanced during geomagnetic storms. Scintillation can cause cycle slips and degrade the positioning accuracy in Global Navigation Satellite System (GNSS) receivers. This paper investigates the correlation between the southward reversals of the interplanetary magnetic field (IMF) Bz and the occurrence of scintillation, along with the consequential impact on the tracking performance of a GNSS receiver located at a high‐latitude station, Bronnoysund (geographic latitude 65°N) in Norway. The analysis revealed that the occurrence of scintillation at this station is largely controlled by the IMF conditions. The receiver tracking performance under strong scintillations is evaluated by the receiver PLL (phase‐locked loop) tracking jitter variance. The dependence of the PLL jitter variance on phase scintillation can be best represented by a quadratic fit.

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL). An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL. We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch. The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply. The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is −89 and −118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset, respectively; and the reference frequency spur is below −77 dBc. The chip size is 0.32 mm2 and the power consumption is 30.6 mW.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

New Phase-Locked Loop Design: Understanding the Impact of a Phase-Tracking Channel Detector

We consider design of a phase-locked loop (PLL) that runs in conjunction with a phase-compensating channel detector capable of tracking and compensating for slow-varying phase errors. The main significance of this highly nontraditional timing recovery structure is that unlike the traditional PLLs, the loop's overall tracking ability and the steady-state jitter performance can be controlled more or less separately. The effective bandwidth of the PLL is set much lower than the traditional PLL for given input phase error fluctuations. As a result, the PLL jitter is made considerably smaller than traditional systems. On the other hand, the tracking ability of the overall loop depends largely on the window parameter associated with the phase estimator operating inside the Viterbi-like trellis detector. The window parameter has only a small effect on the loop jitter. The new PLL design is tested via tracking speed, timing jitter and error rate performance comparisons against a timing recovery method based on traditional PLL design. Simulation results in a turbo equalizer setting are also presented that validate the new PLL design methodology proposed.

A low-noise PLL design achieved by optimizing the loop bandwidth

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Jitter analysis of PLL-generated clock propagation using Jitter Mitigation techniques with laser voltage probing

A new Jitter Mitigation feature in the latest generation laser voltage probing (LVP) tool effectively removes PLL jitter from LVP waveforms [Ng Yin S, Lo W, Wilsher K. Next generation laser voltage probing. In: Proceeding, international symposium on testing and failure analysis; 2008. p. 249]. It facilitates the probing of phase-locked loop (PLL) driven circuitry inside of integrated circuits (ICs). In particular, it allows the detection of small amounts of excess jitter that would normally be masked by the much larger jitter of the PLL. To demonstrate the practical application of this Jitter Mitigation feature, we report on the jitter analysis of a PLL-generated clock signal as it propagates, through buffers and logic circuitry, to an external I/O pad of an IC. The IC was a 0.9 V, 65 nm technology graphics processing unit (GPU). The analysis was to determine where excess jitter was introduced into the clock path when the GPU was electrically stressed. Details of the jitter analysis, including Jitter Mitigation methodology, probing setup, and results of the timing measurements, will be presented in this paper.

JITTER ANALYSIS AND PREDICTION FOR PHASE LOCKED LOOPS UTILIZING FERROELECTRIC CAPACITORS

ABSTRACT The non-linear nature of charge versus polarization in ferroelectric capacitors offers the unique opportunity to minimize jitter in phase locked loops (PLL). During the low effective capacitance state, the clock generation signal within the PLL has a high slew rate offering excellent timing characteristics. During the rest of the clock period, the high effective capacitance state is used to average inherent PLL noise. In this paper, we present the improved jitter that results when a PLL is implemented utilizing a strontium bismuth tantalate niobate based ferroelectric capacitor compared to conventional linear capacitor. In addition, we present the analysis of jitter in terms of capacitance characteristics of ferroelectric capacitor. When integrated on CMOS technology, PLLs based on ferroelectric capacitors have great potential for producing reduced jitter clock sources usable in future clock recovery and communication circuits.

PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element

Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.

Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.

Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

Notice of Violation of IEEE Publication Principles<br><br>"A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation"<br>by Maxim, A.<br>in the IEEE Journal of Solid-State Circuits,<br>Volume 40, Issue 1, Jan. 2005 Page(s):110 - 131<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references. <br/> This paper presents a multigigahertz active clock deskewing architecture that uses analog phase interpolation to replace the area-consuming capacitively controlled delay lines used in regional clock deskewing delay-locked loops. It provides a small phase step that is uniform and process-independent over the entire 2ϖ phase deskew range, which reduces the intra-die clock skew. The phase interpolators have virtually zero latency, which leads to a very fast clock deskewing process and allows for the tracking of fast dynamic variations. A bandgap referencing technique was used to provide a tracking mechanism between the phase-locked loop (PLL) time constants to achieve a process-independent PLL damping factor and pole-zero separation. Both feedback and input divider modulus independence of the damping factor was achieved through a combined current and capacitor switching architecture, that provides an optimal compromise between area, power, and spurs. A reset-generation charge-pump architecture was introduced to minimize the dead-zone avoidance pulse width in order to improve the PLL jitter and reference spurs performance. The power supply partitioning exploits the dual gate oxide transistors offered by the current deep-submicron CMOS technologies. The biasing scheme is comprised of a 1.5-V supply for the ring oscillator and digital circuitry for speed considerations, while the analog front-end is biased from a 2.5-V supply to ensure more voltage headroom as required by low-gain oscillators and low-noise loop filters.

Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

Time-to-voltage converter for on-chip jitter measurement

In this paper, we present the concept and design of a time-to-voltage converter (TVC), and demonstrate its application to on-chip phase-locked loop (PLL) jitter measurement. The TVC operates in an analog, continuous mode without using a sampling clock. It compares the signal under measurement with a reference signal by charging and discharging a capacitor. First, the low-frequency reference signal charges the capacitor in one cycle. Then, the jitter signal discharges the same capacitor repeatedly until the voltage on the capacitor falls below a threshold. The number of times the jitter signal needs to discharge the capacitor is recorded on a binary counter. We demonstrated that a 160-ps injected jitter is successfully measured by the proposed TVC with a 2-MHz reference signal. We also demonstrated the successful measurement of a 14-ps average PLL jitter, without jitter injection. An 8% measurement error is found in both experiments, using four-bit counters. Finally, we analyze the relations between design parameters and show trade-offs between measurement resolution and measurement time.

A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS

A fully integrated subpicosecond jitter phase-locked loop (PLL)-based frequency synthesizer in a standard digital 0.12-μm CMOS technology with 1.5-V supply is presented. Two differentially tuned LC-VCOs are implemented to support different standards for serial data transmission. A fully differential charge pump and an active loop filter are used for reduction of charge-pump current mismatch. Operating with a 311-MHz reference clock, the PLL achieves typically 860-fs integrated jitter, and a phase noise of -115 dBc/Hz at 1-MHz offset, on a 2.488-GHz output. The power consumption is 35 mW, and the area is 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Analysis of jitter in phase-locked loops

Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first- and second-order. Theoretical analysis is supported by results obtained using mixed-signal behavior simulation.

Measurements and analysis of PLL jitter caused by digital switching noise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-/spl mu/m digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons.