JITTER ANALYSIS AND PREDICTION FOR PHASE LOCKED LOOPS UTILIZING FERROELECTRIC CAPACITORS

Abstract

ABSTRACT The non-linear nature of charge versus polarization in ferroelectric capacitors offers the unique opportunity to minimize jitter in phase locked loops (PLL). During the low effective capacitance state, the clock generation signal within the PLL has a high slew rate offering excellent timing characteristics. During the rest of the clock period, the high effective capacitance state is used to average inherent PLL noise. In this paper, we present the improved jitter that results when a PLL is implemented utilizing a strontium bismuth tantalate niobate based ferroelectric capacitor compared to conventional linear capacitor. In addition, we present the analysis of jitter in terms of capacitance characteristics of ferroelectric capacitor. When integrated on CMOS technology, PLLs based on ferroelectric capacitors have great potential for producing reduced jitter clock sources usable in future clock recovery and communication circuits.