Abstract
The reduction of timing jitter has become a primary goal in the design of Phase Locked Loops (PLLs) and Delay Locked loops (DLLs) for high data rate systems. Timing jitter causes a decrease in timing margin and reduces the maximum achievable frequency of operation for digital circuits. This paper proposes a capacitor compensation scheme to reduce accumulated jitter in PLLs. The focus of this investigation is on the reduction of power supply induced noise to the Voltage Controlled Oscillator (VCO). For a 250MHz PLL designed in 0.13um CMOS technology the long term accumulated jitter was simulated at 1.3ns peak to peak which reduced to 750ps peak to peak after the addition of our compensation scheme.
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