Jet Vapor Deposition Research Articles

BOEMDET-Band Offsets and Effective Mass Determination Technique applied to MIS devices on silicon to obtain the unknown bandgap of insulators

The Fowler-Nordheim carrier tunneling slope constants for electron and hole conduction through MOS devices fabricated on silicon substrate can be utilized to determine the conduction and valence band offsets, carrier effective masses in the SiO2 and its unknown bandgap, independent of photoemission spectroscopic measurements of band offsets on SiO2/Si samples. The slope constants can be obtained from the electron and hole tunneling currents versus oxide voltage characteristics on a pair of n-MOS and p-MOS devices in accumulation. This characterization technique called BOEMDET, can be applied to other insulating materials grown or deposited on silicon, such as jet vapor deposited (JVD) nitride, HfSiON, SiOxNy, AlN, BN, high-K oxides, and transparent conducting oxides (TCO).

Kinetics of Dissolution and Isothermal Solidification for Gold-Enriched Solid–Liquid Interdiffusion (SLID) Bonding

This paper presents the development and characterization of a fluxless die-attach soldering process based on gold-enriched solid–liquid interdiffusion (SLID). Eutectic Au-Sn and pure Au were deposited by jet vapor deposition (JVD) onto two substrates, assembled in a sandwiched structure, and processed in a vacuum furnace using different temperatures and times. Microstructural characterization, based on scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy (EDS) analysis, revealed the formation of sound joints governed by the interdiffusion of the main constituents. Kinetic studies for the dissolution and the isothermal solidification stages were conducted. Differential scanning calorimetry (DSC) revealed a solder joint that is thermally stable up to 498°C, thus demonstrating the effectiveness of using the SLID process for the production of joints which require a lower processing temperature compared with their remelting point. Based on these findings, the recommended final bonding parameters are processing temperature and time of 340°C (310°C < TP < 340°C) and 5 min, respectively.

Thermal Stability Characterization of the Au–Sn Bonding for High-Temperature Applications

There is a need for electromechanical devices capable of operating in high-temperature environments (>200°C) for a wide variety of applications. Today's wide-bandgap semiconductor-based power electronics have demonstrated a potential of operating above 400°C, however, they are still limited by packaging. Among the most promising alternatives is the Au-Sn eutectic solder, which has been widely used due to its excellent mechanical and thermal properties. However, the operating temperature of this metallurgical system is still limited to ~250°C owing to its melting temperature of 280°C. Therefore, a high-temperature-resistant system is much needed, but without affecting the current processing temperature of ~325°C, typically exhibited in most high-temperature Pb-free solders. In this paper, we present the development and characterization of a fluxless die-attach soldering process based on gold-enriched solid-liquid interdiffusion (SLID). A low-melting-point material (eutectic Au-Sn) is deposited in the face of a substrate, whereas a high-melting-point material, gold in this instance, is deposited in its mating substrate. Deposition of all materials was performed using a jet vapor deposition (JVD) equipment where thicknesses are controlled to achieve specific compositions in the mixture. Sandwiched coupons are isothermally processed in a vacuum reflow furnace for different reflow times. Post-processed samples confirm the interdiffusion mechanism as evidenced by the formation of sound joints that prove to be thermally stable up to ~490°C after the completion of the SLID process. Differential scanning calorimetry demonstrate the progression of the SLID process by quantifying the remaining low-melting-point constituent as a function of time and temperature, this serving as an indicator of the completion of the soldering process. Mechanical testing reveals a joint with shear strength varying from 39 to 45.5 MPa, demonstrating to be stable even after 500 h of isothermal aging. Moreover, these investigations successfully demonstrate the use of the Au-Sn SLID system and the JVD technology as potential manufacturing processes and as a lead-free die-attach technology.

Microstructural Evolution and Thermal Stability Characterization of a High Temperature Die Attach Lead-Free System

There is a need for electromechanical devices capable of operating in high temperature environments (&amp;gt;200°C) for a wide variety of applications. Today's wide-bandgap (WBG) semiconductor based power electronics have demonstrated a potential of operating above 400°C, however they are still limited by packaging. Among the most promising alternative is the Au-Sn eutectic solder, which have been widely used due to its excellent mechanical and thermal properties. However, the operating temperature of this metallurgical system is still limited to ∼250°C owing to its melting temperature of 280°C. Therefore, a higher temperature resistant system is much needed, but without affecting the current processing temperature of ∼325°C typically exhibited in most high temperature Pb-Free solders. This paper presents the development and characterization of a fluxless die attach soldering process based on gold enriched solid liquid inter-diffusion (SLID). A low melting point material (eutectic Au-Sn) was deposited in the face of a substrate, whereas a high melting point material, gold in this instance, was deposited in its mating substrate. Deposition of all materials was performed using a jet vapor deposition (JVD) equipment where thicknesses were controlled to achieve specific compositions in the mixture. Sandwiched coupons where isothermally processed in a vacuum reflow furnace. SEM and EDS were employed to reveal the microstructural evolution of the samples in order to study the interfacial reactions of this fluxless bonding process. Mechanical characterization of the each individual intermetallic phase was achieved by nanoindentation. Differential scanning calorimetry demonstrated the progression of the SLID process by quantifying the remaining low melting point constituent as a function of time and temperature. Post-processed samples confirmed the inter-diffusion mechanism as evidenced by the formation of sound joints that proved to be thermally stable up to ∼490°C after the completion of the SLID process.

Metal-insulator-semiconductor structure on low-temperature grown GaAs

The metal-insulator-semiconductor (MIS) capacitors on low-temperature grown (LTG) GaAs were made using the jet-vapor-deposition (JVD) silicon nitride as the gate dielectrics. The unpinned JVD-SiN/LTG-GaAs interface was shown by the capacitance-voltage characterization. The observed Fermi level “pinning” in the unannealed samples was caused by the bulk point defects in LTG GaAs. Annealing reduced the bulk defect density in LTG GaAs and revealed the intrinsically unpinned Fermi level at the interface. The result is consistent with the expected unpinning of LTG GaAs surface, and JVD SiN appears to play a critical role to enable this unpinned interface. JVD SiN showed low leakage current (∼10nA∕cm2 at 2MV∕cm) and high breakdown electric field (∼9.8MV∕cm), promising for MIS device applications.

High-temperature phase stability of hafnium aluminate films for alternative gate dielectrics

Hafnium aluminate films with different compositions were deposited at room temperature by jet vapor deposition. The as-deposited films were amorphous. After annealing at 1100 °C, the microstructure of the films was analyzed by high-resolution transmission electron microscopy, electron diffraction and electron energy loss spectroscopy (EELS). The crystalline phase in pure HfO2 films was monoclinic. With an increase in the Al content in the films, the amount of metastable HfO2 with a tetragonal distorted fluorite structure increased. In addition, the grain sizes decreased, making the detection of crystallization by x-ray diffraction difficult. No crystalline Al2O3 phase could be unambiguously detected in electron diffraction patterns in films with up to 30 mol % Al2O3. However, an Al-rich intergranular phase was identified by EELS. Films with ∼64 mol % Al2O3 crystallized as tetragonal HfO2 and metastable cubic Al2O3 with the spinel structure. The complex microstructures of the films should be considered in the interpretation of their dielectric and electrical properties after high temperature anneals.

Stress Voltage Polarity Dependence of JVD-&amp;lt;tex&amp;gt;$hboxSi_3 hboxN_4$&amp;lt;/tex&amp;gt;MNSFET Degradation

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.

Gate dielectrics for Si, SiC, and GaN as synthesized by jet vapor deposition

The principle of the Jet-Vapor Deposition (JVD) technique for thin dielectric deposition will be introduced, the properties of JVD silicon nitride (SiN), silicon oxide, and oxide/nitride/oxide (ONO) stacks as MOS gate dielectrics for Si, SiC, and GaN will be presented.

A new method to characterize border traps in submicron transistors using hysteresis in the drain current

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n/sub BT/ is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.

JVD silicon nitride as tunnel dielectric in p-channel flash memory

High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO/sub 2/ tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown.

Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

AbstractWe have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI–MOSFETs

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si/sub 3/N/sub 4/ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO/sub 2/ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si/sub 3/N/sub 4/ barrier (2.1 eV) is lower than the Si-SiO/sub 2/ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO/sub 2/ MOSFETs.

High-quality oxide/nitride/oxide gate insulator for GaN MIS structures

We report on a SiO/sub 2//Si/sub 3/N/sub 4//SiO/sub 2/ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450/spl deg/C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150/spl deg/C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs.

Pyroelectric characteristics of thin PbTiO3 and la-modified PbTiO3 films on platinum films for infrared sensors

In this work, we grew lead titanate (PbTiO3) and La-modified PbTiO3 thin films on platinized silicon (Si(100)) substrates under controlled substrate temperature and ambient by a modified jet-vapor deposition (JVD) process described in this paper. The x-ray diffraction patterns obtained from these films showed a single-phase perovskite structure. We examined locally homogeneity and thickness of these films through the comparative use of laser Raman spectroscopy. We also collected Raman and x-ray data on pure PbTiO3, as well as prepared lead zirconate titanate (PZT) (54/46), and PZT (50/50) films using the JVD process. This paper discusses the temperature variations of the pyroelectric and dielectric properties of three compositions of La-modified PbTiO3 films containing 5.2% to 15% of La, respectively, with a view toward studying the effect of La in place of Pb on these electrical properties. We detected significant pyroelectric currents on all three La-modified PbTiO3 films before performing poling treatments, and observed pyroelectric coefficeints as high as 84 nC/cm2·°C in the poled La-doped PbTiO3 films containing 5.2% La. The pyroelectric coefficient and dielectric constant varied significantly with La content. We compared the calculated figures of merit, which were based on the measured physical properties, with pure PbTiO3 as well as PZT and lead lanthanide zirconate titanate (PLZT) films. These properties just described illustrate that these films would be suitable for IR detectors.

Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics

The degradation of 100-nm effective channel length pMOS transistors with 14 /spl Aring/ equivalent oxide thickness Jet Vapor Deposition (JVD) Si/sub 3/N/sub 4/ gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 /spl Aring/ Si/sub 3/N/sub 4/ transistors is compared to reliability of 16 /spl Aring/ SiO/sub 2/ transistors.

Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

“Jet Vapor Deposition”, a novel vacuum coating technique with superior properties

Dry coating technologies offer the steel industry a wide range of new possibilities. In this context, CRM develops a new process for evaporation under vacuum : the JVD (Jet Vapor Deposition).

Transmission electron microscope investigation of SrBi2Ta2O9 memory capacitors on Si with silicon dioxide and silicon nitride as buffers

Ferroelectric memory capacitors were made by deposition of SrBi2Ta2O9 (SBT) on Si with thin (∼40–90 Å) buffer layers of jet vapor deposition (JVD) silicon nitride and oxide. Transmission electron microscope analysis was carried out to compare the microscopic integrity of both films after subsequent processing steps. It was found that the thin SiO2 buffer layer failed to prevent further oxidation of the Si substrate and furthermore allowed the diffusion of the SBT towards the SiO2/Si interface. In contrast the silicon nitride layer deposited by the JVD process acted as a good barrier for the diffusion of SBT. It also stopped further oxidation of the Si substrate during subsequent annealing in oxygen. Electrical tests show that the capacitors have large memory windows and that the windows present only slight degradation after 1011 switching cycles. The use of JVD nitride as a buffer is encouraging for the further development of ferroelectric memory transistors.

Highly robust ultrathin silicon nitride films grown at low-temperature by microwave-excitation high-density plasma for giga scale integration

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400/spl deg/C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation.